Abstract: A protective envelope, made of a plastics material for enclosing a semiconductor integrated circuit, includes a flattened parallelepiped body having a sidewall formed of first and second portions set to converge toward each other. The envelope also includes a lead frame embedded in the body and bearing the integrated circuit, the lead frame having a section bent to form a baffle plate orientated toward the first sidewall portion. Advantageously, the bent section of the lead frame has a plane end edge extending parallel to the first sidewall portion at a spacing therefrom.

Abstract: A vacuum package for integrated circuit devices includes a sealing ring having multiple control spacers of uniform thickness distributed around the sealing ring. The sealing ring is in a designated area on a substrate, material and surrounds one or more integrated circuit devices. The vacuum package also includes a sealing layer on the sealing ring. A vacuum package lid is sealed to the sealing ring by the sealing layer on the sealing ring. The vacuum package lid provides a vacuum cell for the one or more integrated circuit devices.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: A lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.

Abstract: A semiconductor device having a unit lead frame defining a support with a peripheral edge and a first lead spaced from the peripheral edge. The first lead has a recess formed therein. A semiconductor chip is provided on the support. A conductive element electrically connects between the semiconductor chip and the first lead. The resin layer on the semiconductor chip and the first lead extends into the recess. The invention is also directed to a unit lead frame that is part of the semiconductor device, a lead frame incorporating a plurality of unit lead frames, and a method of manufacturing semiconductor devices.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.

Abstract: The present invention provides a packaged chip that includes at least one dam disposed between the chip and interposer, blocking an encapsulant flow path in the package formed by the assembly of the interposer and chip. In one preferred embodiment, the dam comprises a lead-like structure formed on the interposer that closes an encapsulant flow path in the package. The invention further provides a novel interposer that may be assembled with a chip into the novel packaged chip. Methods are also provided for making the packaged chip and the interposer.

Abstract: The present invention provides a packaged chip that includes at least one dam disposed between the chip and interposer, blocking an encapsulant flow path in the package formed by the assembly of the interposer and chip. In one preferred embodiment, the dam comprises a lead-like structure formed on the interposer that closes an encapsulant flow path in the package. The invention further provides a novel interposer that may be assembled with a chip into the novel packaged chip. Methods are also provided for making the packaged chip and the interposer.

Abstract: A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air vent in a mold. After a semiconductor chip is mounted on the substrate by a plurality of conductive elements, a molding compound having high fluidity and fine filler particles is used to encapsulate the chip and the flash preventing mechanism. As the flash preventing mechanism is disposed in a manner of reducing the entry space of the air vent, the flow of the molding compound is impeded by the flash preventing mechanism, making the molding compound rapidly absorb heat of the mold and accordingly increased in viscosity. This helps prevent flash of the molding compound from occurrence, and assure the semiconductor package in quality and profile.

Abstract: A semiconductor device includes a substrate, and the substrate is formed with a wiring pattern on its surface. The wiring pattern includes electrodes, wire-bonding (WB) pads and connecting portions for connecting the electrodes and the WB pads. The WB pads are so formed that the lengthwise directions thereof are in parallel or approximately in parallel to lines, in radiative form, extending from the center of a die-bonding (DB) area. Accordingly, if a chip having a first size is die-bonded within the DB area, bonding wires become approximately in parallel to the lengthwise directions of the WB pads. Even if a chip having a second size smaller than the first size but the same shape is die-bonded, the bonding wires are also in parallel to the lengthwise directions of the WB pads. Thus, since one substrate can be used regardless of the size of a chip, there is no need to prepare a plurality of wiring patterns for each size of chips.

Abstract: A semiconductor device includes an interposing substrate having a top surface mounting thereon a semiconductor chip and a bottom surface mounting thereon a solder ball islands. Chip electrodes of the semiconductor chip are connected to the solder ball islands through a top interconnect pattern, via holes and a bottom interconnect pattern. The second interconnect pattern has a solder-flow damping/stopping pattern in the vicinity of the solder ball islands for stopping the solder from flowing onto the bottom interconnect pattern upon melting.

Abstract: In a semiconductor device, an island penetrating hole, which is larger than a mounted chip, is formed on an island of a lead frame, and a heatsink is mounted on the island so as to cover the island penetrating hole. The chip is disposed on a surface of the heatsink in the island penetrating hole. The ground terminal of the chip and the island are wire-bonded to each other via GND wires. This arrangement makes it possible to reduce a heat resistance in a heat-releasing path, thereby improving a heat-releasing property. Further, the GND wires are shortened and a GND inductance is reduced. Consequently, it is possible to efficiently exert capability of the chip.

Abstract: A lead frame for semiconductor device comprising inner leads, outer leads, and dam bars, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of a semiconductor chip to be mounted on the lead frame, and the inner lead having a first end and a second end, the first ends of the respective inner leads being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads being arranged into arrays at opposed sides of the lead frame, to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged to have lengths between the first and the second ends which are substantially equivalent to each other. A semiconductor device using the lead frame is also disclosed.

Abstract: Interposers having an encapsulant fill control feature are disclosed. In one embodiment, an interposer includes a substrate having a first surface proximate the semiconductor component, and a fill control feature projecting from the first surface toward a region adapted to be occupied by a semiconductor component. The fill control feature is positioned between the region and the substrate and is sized to at least partially block an opening between a semiconductor component that may be positioned in the region and the first surface. As an encapsulant material is flowed about the semiconductor component, the fill control feature at least partially blocks the encapsulant material from entering the opening. The encapsulant material may then substantially surround the semiconductor component, after which the encapsulant material may substantially fill a space between the semiconductor component and the interposer.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in an LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air vent in a mold. After a semiconductor chip is mounted on the substrate by a plurality of conductive elements, a molding compound having high fluidity and fine filler particles is used to encapsulate the chip and the flash preventing mechanism. As the flash preventing mechanism is disposed in a manner of reducing the entry space of the air vent, the flow of the molding compound is impeded by the flash preventing mechanism, making the molding compound rapidly absorb heat of the mold and accordingly increased in viscosity. This helps prevent flash of the molding compound from occurrence, and assure the semiconductor package in quality and profile.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A semiconductor device includes a circuit board on which a semiconductor chip is mounted via an adhesive resin layer and through which a moisture drain hole is formed. A pit part having a width wider than a diameter of the moisture drain hole is formed in a part of the adhesive resin layer exposed in the moisture drain hole. On this account, the semiconductor device can properly drain moisture to the outside when the semiconductor device is mounted on another packaging substrate by reflowing.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: The lead frame of the present invention is a lead frame used in resin encapsulation of a semiconductor chip using an encapsulation mold that includes a die cavity to be filled with an encapsulation resin, the lead frame including: a first region exposed to the die cavity; a second region that is surrounding the first region and to be clamped by the encapsulation mold; a third region exposed to an ambient air with the die cavity being filled with the encapsulation resin; and at least one groove formed on a surface of the lead frame that is opposite to another surface of the lead frame on which the first region is present, the at least one groove extending from an area corresponding to the first region across another area corresponding to the second region so as to reach the third region.

Abstract: Disclosed is a semiconductor package capable of realizing a small and compact size and improving the reliability and the fabrication method of the same. The disclosed comprises: a main semiconductor chip having a plurality of main chip pads and operating as a lead frame or a substrate; a plurality of metal patterns electrically connected to each corresponding main chip pad and having electrodes formed on both ends; one or more sub semiconductor chip adhered to the main semiconductor chip by adhering bumps formed on a plurality of sub chip pads to each corresponding electrode; a dam formed on the main semiconductor chip in a shape surrounding the inner electrodes except for the outer electrodes on the outmost region of the main semiconductor chip; filling materials filled up in the dam; and a plurality of solder balls adhered on the outmost electrodes.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g.

Abstract: A method and apparatus for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is less in thickness than the tape base material 1a, while sealing by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, let the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a be identical to a stress neutral plane of the TCP as a whole.

Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.

Abstract: A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.

Abstract: An FBGA packaged device including a die adhered to a substrate with a small gap being formed between the die and substrate. An opening is formed through the substrate adjacent the center portion of the die. An encapsulating mold is formed around the die extending into the gap and also filling the channel. At least one barrier is disposed in the gap between the substrate and the die adjacent the channel to control the flow path of the encapsulating material as the mold is formed in the package.

Abstract: A circuit pattern tape for the wafer-scale production of chip size semiconductor packages is adapted to be laminated onto a semiconductor wafer and includes a flexible insulating layer, a plurality of identical circuit pattern units arrayed thereon, and a solder mask covering the circuit patterns. Each circuit pattern unit includes a central opening, a plurality of bond fingers arranged on opposite sides of the opening and electrically connected through the opening to associated die pads on an underlying semiconductor chip in the wafer, a plurality of solder ball lands, each having a solder ball attached thereto, and a plurality of conductive traces electrically connecting respective ones of the bond fingers and the solder ball lands to each other.

Abstract: Upper and lower protective protruded portions are formed on an upper and lower surfaces of the lead frame to prevent breakage of resin mold or bending of terminals of semiconductor devices 2 mounted on a lead frame 1 during transportation of the lead frame between fabrication steps thereof. The regions of the upper and lower protective protruded portions are located between adjacent ones of the semiconductor devices. Those protruded portions are formed simultaneously with the resin sealing of the semiconductor devices by using the same resin material.

Abstract: A method for producing a chip module includes punching a chip carrier to form a chip carrier fixing section and chip carrier contact sections spaced apart from the chip carrier fixing section by slots defining a given distance. The given distance is subsequently reduced to a dimension preventing a flow through of a sealing mass by a swaging operation carried out at least in a region close to the slots.

Abstract: A lead frame of the present invention is a lead frame used for the production of semiconductor package, wherein each of terminals to be wire-bonded of the lead frame between electrodes provided on the top surface of semiconductor device mounted on a die pad and the terminals has one or two groove(s) for limiting plating area of noble metal for wire-bonding. A semiconductor package of the present invention is produced using the lead frame. Since grooves are provided in each terminal, the accuracy of plating area can be easily checked by visual observation. Accordingly, the cut of inspection cost can be carried out. Further, the grooves absorb stress applied to terminal when molded semiconductor packages are separated individually from each other by means of punching or dicing. Accordingly, coming off of molding compound from terminal is prevented.

Abstract: An improved leadframe-based CSP and a method of forming the leadframe-based CSP are provided. The leadframe-based CSP includes a leadframe including a die attach pad and a plurality of wire bonding pads, at least one aperture disposed in the die attach pad, at least one die on the die attach pad, at least one bonding wire for electrically connecting the die and the wire bonding pads, and a mold compound for encapsulating the die and the bonding wire to form a chip package, wherein the mold compound is formed in the aperture.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.

Abstract: A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Abstract: A lead frame including signal-connecting leads, a die pad and support leads is provided. A semiconductor chip is bonded to the die pad with an adhesive. The semiconductor chip, electrode pads and the signal-connecting leads are electrically connected to each other with metal fine wires. And these members are encapsulated in a resin encapsulant. The back surface of the die pad is subjected to half etching or the like to form a convex portion and a flange portion surrounding the convex portion. Since a thin layer of the resin encapsulant exists under the flange portion, the resin encapsulant can hold the die pad more strongly and the moisture resistance of the device can be improved with the lower surface of the die pad protruding from the resin encapsulant. As a result, the characteristics of a resin-molded semiconductor device having a die pad exposed on the back surface of a resin encapsulant can be improved.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a semiconductor package based on window pad type of leadframe. The proposed semiconductor packaging technology is characterized by the mounting of a window shim having a solid ring portion and a hollowed window portion over the die pad of the leadframe. The window shim is dimensioned in such a manner that the width of the ring portion thereof is larger than the width of the window portion of the die pad of the leadframe, while the width of the window portion of the window shim is smaller than the width of the semiconductor chip. This feature allows one design of the window pad type of leadframe to be universally suited for packaging semiconductor chips of various sizes. Moreover, the incorporation of the window shim additionally allows an increase in the heat-dissipation efficiency of the packaged chip.

Abstract: A BGA semiconductor package having an embedded heat sink is proposed. The heat sink mounted on a substrate includes a flat portion and supporting members for supporting the flat portion to be positioned above a semiconductor chip. The flat portion is formed with at least one taper air vent for ventilating air in a gap between the flat portion and the chip during a molding process. This further helps prevent voids from forming in an encapsulant due to the air trapped in a molding resin as being flowing slowly through the gap, and avoid the occurrence of a popcorn effect on the encapsulant during a temperature cycle in subsequent processes. As a result, quality and yield for the packaged products can be significantly improved.

Abstract: A protection device for integrated circuits which prevents inadvertent damage caused by over-voltage power surges. The protection device comprising an insulating carrier having a ground plane thereon and a plurality of conductive pads around a periphery thereof. The plurality of conductive pads are spaced from the ground plane with a precision gap therebetween. When the protection device is placed over the integrated circuit chip, the plurality of conductive pads are coupled to the bonding pads of the integrated circuit and at least one of the conductive pads is coupled to the ground plane.

Abstract: A BGA semiconductor package having an embedded heat sink is proposed. The heat sink mounted on a substrate includes a flat portion and supporting members for supporting the flat portion to be positioned above a semiconductor chip. The flat portion is formed with at least one taper air vent for ventilating air in a gap between the flat portion and the chip during a molding process. This further helps prevent voids from forming in an encapsulant due to the air trapped in a molding resin as being flowing slowly through the gap, and avoid the occurrence of a popcorn effect on the encapsulant during a temperature cycle in subsequent processes. As a result, quality and yield for the packaged products can be significantly improved.

Abstract: In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.

Abstract: A leadframe and molded semiconductor package made using the leadframe are disclosed. The leadframe includes leads extending from a dam bar toward a central chip mounting region. A pseudo tie bar extends diagonally from three of the four corners of the dam bar toward the chip mounting region. A resin introduction slot is at the remaining corner of the dam bar. The resin introduction slot is wider than a space between adjacent leads. The leads adjacent to the resin introduction slot increase in width as they extend from the dam bar toward the chip mounting region. The leadframe is used to form a semiconductor package having a package body formed of a molded resin. The leadframe design minimizes voids and damage caused by the molding process.

Abstract: A quad flat non-leaded package leadframe for supporting a die in a semiconductor package. The leadframe includes a plurality of packaging unit. Each packaging unit has a plurality of leads around a central region. Each pair of neighboring packaging unit is connected by a dam bar. The connected regions between the dam bar and the leads of each neighboring packaging unit have a thickness smaller than the other regions.

Abstract: An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Abstract: A disturbing plate structure having at least one down set, applicable in a lead frame-type package in a semiconductor. The disturbing plate has at least a lead frame, a die, a glue layer, a plurality of disturbing plates, a top mold compound, and a bottom mold compound. The lead frame has a plurality of leads. Two disturbing plates are located on two sides of the die. A space is formed by bending a first bent portion and a second bent portion of the disturbing plate down. Finally, the lead frame is encapsulated with a mold compound. By adjusting the size of the space formed by the first bent portion and the second bent portion, the top mold compound section has substantially the same volume as the bottom mold compound section to finish the packaging and forming.