Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead tip and a lead body, forming a recess in the lead body from a lead body top surface, connecting an integrated circuit die and the external interconnect, and molding the external interconnect with the recess filled.

Abstract: A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip.

Abstract: A light emitting device includes: a light emitting element; a first lead including a recess in one end portion, the recess including a first bottom surface with the light emitting element bonded thereto, at least one of a through hole and a notch, and a light shielding portion capable of suppressing leakage of emitted light from the light emitting element from the one of the through hole and the notch; a second lead opposed to the first lead; and a molded body filling the one of the through hole and the notch, covering the light emitting element, embedding at least part of the first lead and at least part of the second lead, and made of a translucent resin.

Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.

Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.

Abstract: A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and conductive connections (212) span from the chip to the aluminum of the lead segments. Polymeric encapsulation material (220), such as a molding compound, covers the chip, the connections, and portions of the aluminum lead segments without leaving cantilevered segment portions. Preferably by electroless plating, a zinc layer (301) and a nickel layer (302) are on those portions of the lead segments, which are not covered by the encapsulation material including the aluminum segment surfaces (at 203b) formed by the device singulation step, and a layer (303) of noble metal, preferably palladium, is on the nickel layer.

Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device comprises a semiconductor chip including a silicon substrate, a die pad to which the semiconductor chip is secured through a first solder layer, a resin-encapsulating layer encapsulating the semiconductor chip, and lead terminals electrically connected to the semiconductor chip and including inner lead portion covered with the resin-encapsulating layer. The lead terminals are made of copper or a copper alloy. The die pad is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals.

Abstract: A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.

Abstract: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes a first semiconductor die attached the first die attach pad at the first side of the leadframe structure, and a second semiconductor die attached to the second die attach pad at the second side of the leadframe structure. The semiconductor die package further includes a housing material covering at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: Disclosed are packages for optocouplers and methods of making the same. An exemplary optocoupler comprises a substrate having a first surface and a second surface, a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's first surface, and a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's second surface. The substrate may comprise a pre-molded leadframe, and electrical connections between optoelectronic dice on opposite surfaces of the substrate may be made via one or more leads of the leadframe.

Abstract: A semiconductor device comprises a support member having a pair of first conductive materials and a pair of second conductive materials on an insulating substrate, and a sealing member covering a semiconductor element arranged on the support member, wherein the support member has an insulating portion where the insulating substrate is exposed between the pair of the first conductive materials, and at least one of the pair of the second conductive materials is arranged along the side of the insulating portion, and the sealing member is disposed so that the sealing member is over at least a part of at least one of the first conductive materials and the second conductive materials.

Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.

Abstract: A mounting structure for a semiconductor element is disclosed. The semiconductor element is bonded to a die pad through an adhesive film, which is formed by applying a predetermined amount of a paste adhesive onto the surface of the die pad and placing the semiconductor element on the die pad so as to press and spread the adhesive between the lower surface of the semiconductor element and the die pad. A wire extends between the semiconductor element and a terminal pad disposed around the die pad. The die pad includes plural grooves in the surface thereof. Each of the grooves extends from the center of the die pad toward a peripheral edge of the die pad and ends at the inner side of the peripheral edge of the die pad.

Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described.

Abstract: A semiconductor package includes a wiring board having a plurality of first electrode pads exposed on a top surface thereof, and a plurality of second electrode pads exposed on a bottom surface thereof, and the first electrode pads are electrically connected to the respective second electrode pads. A semiconductor device is mounted on the top surface of the wiring board, and includes an endless ring-shaped resistance circuit formed in an interior of the device along a periphery thereof, and a plurality of third electrode pads provided inside the resistance circuit and electrically connected to the resistance circuit. The third electrode pads are electrically connected to the first electrode pads, respectively. A sealing resin layer is formed over the first surface of the wiring board so that the device and the first electrode pads are sealed and protected by the sealing resin layer.

Abstract: Broadly speaking, the present invention fills these needs by providing a lead frame package including a substrate stack having opposed sides, one of which includes a plurality of signal traces, with the remaining side including a ground plane. An integrated circuit is mounted to the substrate stack. The integrated circuit includes a plurality of bond pads. A plurality of leads is in electrical communication with a subset of the plurality of signal traces. A plurality of electrically conductive elements placing a sub-group of the plurality of bond pads in electrical communication with a sub-part of the plurality of electrically leads by being bonded signal traces of the subset, spaced-apart from the plurality of leads.

Abstract: A first lead frame group is constituted by a plurality of lead frames that are connected to the first circuit, terminals of the plurality of lead frames being provided on a first side of the semiconductor device. A second lead frame group is constituted by a plurality of lead frames that are connected to the second circuit, terminals of the plurality of lead frames being provided on a second side of the semiconductor device. A suspension lead for suspending a die pad that supports the semiconductor chip, the suspension lead being arranged from a corner portion that is formed by the first side and the second side toward the semiconductor chip. Among a group of the terminals of the first lead frame group that are provided on the first side, a terminal on the corner portion side is a terminal for inputting or outputting a signal with a high frequency.

Abstract: A QFN package is provided with a lead frame formed by processing a copper alloy sheet containing 0.01 to 0.50% by mass Fe, 0.01 to 0.20% by mass P, and Cu and inevitable impurities as other components, having a micro Vickers hardness of 150 or above, a uniform elongation of 5% or below and a local elongation of 10% or below, or a copper alloy sheet containing 0.05 to 2% by mass Ni, 0.001 to 0.3% by mass P, 0.005 to 5% by mass Zn, and Cu and inevitable impurities as other components, having a micro Vickers hardness of 150 or above, a uniform elongation of 5% or below and a local elongation of 10% or below. Lead burrs formed during the dicing of the QFN package are short, and a dicing blade used for dicing the QFN package is abraded at a low wear-out rate.

Abstract: An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.

Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.

Abstract: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.

Abstract: Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.

Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include bottom surface portions which, in the completed semiconductor package, are exposed and at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body in the completed semiconductor package. The semiconductor package also includes one or more power bars and/or one or more ground rings which are integral portions of the original leadframe used to fabricate the same.

Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.

Abstract: A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract: Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: A redistributed lead frame for use in a molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attach sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A semiconductor light emitting device has an outer lead disposed along an outer wall of a mold resin portion perpendicular to a light-emitting plane of a light emitting diode. An outer lead is also disposed at an outer wall of the mold resin portion parallel to and opposite to the light-emitting plane. The outer wall of the resin mold where the outer lead is disposed is taken as a mount face. Each outer wall of the mold resin portion constituting a mount face includes at least one outer lead for an anode and a cathode. According to the present configuration, there is provided a semiconductor light emitting device that allows selection of side-emission mounting or top-emission mounting with the same components on a mount substrate.

Abstract: A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the first surface.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.

Abstract: A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A tape distribution substrate comprises a plurality of distribution lines formed on a base film. In one embodiment, the distribution lines comprise data lines arranged in data line pairs, wherein each data line pair carries a data signal with two different polarities. The distance between the data lines in each data line pair becomes narrower as the data lines extend away from the base film. In another embodiment, the distribution lines comprise power distribution lines, each having a body portion including several holes, and divided into one or more sub-power distribution lines connected to the base film.