Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead (2) formed integral with the package (1) by insert molding, with its one end exposed into the concave portion (1a) and its other end extended from the package (1) to the outside, a sensor chip (3) arranged in the concave portion (1a) for detecting pressure, and a bonding wire (4) electrically connecting the sensor chip (3) and the lead (2) with each other. An interface between the lead (2) and the package (1) on the side of the concave portion (1a) is covered with a first protective resin portion (6) of electrically insulating property, and the bonding wire (4) is covered with a second protective resin portion (7) that is softer than the first protective resin portion (6).

Abstract: A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. The first conduction terminal being in contact with said metal frame and comprising at least an intermediate frame arranged in contact with said second conduction terminal.

Abstract: A semiconductor package including at least one semiconductor chip and inner leads may be provided. The semiconductor package may include a semiconductor chip. A plurality of inner leads having upper surfaces and lower surfaces, may be electrically connected to the semiconductor chip, and may be spaced apart from the semiconductor chip. A molding resin may fix the semiconductor chip and the inner leads. The upper surfaces of the inner leads may be fixed to the molding resin, the lower surfaces of the inner leads may be exposed from the molding resin, and widths of the lower surfaces of the inner leads may be narrower than widths of the upper surfaces of the inner leads.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: A microelectronic package includes a microelectronic element having contacts, a dielectric element, at least a portion of the dielectric element extending beneath the microelectronic element, and a structure including portions of a lead frame. The structure includes a plurality of terminals and leads formed integrally with the terminals, at least some of the terminals and at least some of the leads being disposed entirely beneath the microelectronic element, and at least some of the contacts being connected to at least some of the terminals by at least some of the leads. The leads and terminals are at least about 50 microns thick.

Abstract: A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than the width of another portion of the lead. A plating layer may be provided on the attaching portion. The lead frame may be implemented in a semiconductor package.

Abstract: The semiconductor laser unit includes: a metal plate having a center portion wider than the remaining portions; a flexible substrate having a first opening; a substrate mounted on the center portion; a semiconductor laser placed on the substrate; a frame having a second opening and fixing the flexible substrate in the state of being bent along from the top surface to both side faces of the metal plate; and an optical element covering the second opening. The flexible substrate is fixed so that the first opening extends over the top surface and both side faces of the center portion.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper side of the semiconductor power switch. The component further includes a leadframe including a die pad and a number of leads disposed on one side of the die pad. A number of connectors extends between the source regions and the source leads such that each source lead is electrically connected to each source region.

Abstract: A lead frame package structure with high density of lead pins arrangement is formed. The lead frame structure includes a die, a plurality of first lead pins and a plurality of second lead pins, wherein the first lead pins and the second lead pins are positioned on at least one side of the die, and are electrically connected to the die. The first lead pins and the second lead pins are selected from a group consisting of J-leads, L-leads and I-leads, and terminals of the first lead pins and terminals of the second lead pins are staggered so that the high density of lead pins arrangement is formed without risking a short circuit.

Abstract: A semiconductor chip package is formed by a first semiconductor chip and a second semiconductor chip, which have electrodes for wiring at surfaces thereof, being integrated and mounted in a state in which reverse surfaces thereof oppose one another. Therefore, two semiconductor chips can be freely combined and mounted regardless of chip sizes thereof, and lengths of wires can be shortened. Thus, a wire-bonding yield can be improved, and a semiconductor package having excellent electric characteristics can be obtained.

Abstract: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle are configured to provide continuity of ground between the circuit board and a chip mounted to the paddle.

Abstract: First alignment marks are provided on a film substrate in a manner that they are located at positions offset from the disposed positions of second alignment marks provided on a semiconductor chip. The amount of expansion or contraction of the film substrate is obtained by measuring the distance between the first alignment marks. Based on the amount of expansion or contraction, the semiconductor chip is shifted with respect to the film substrate and mounted thereon.

Abstract: A method of making a microelectronic package includes providing a lead frame having at least one bus element and a plurality of branches extending from the bus element, each branch including a terminal and an elongated lead extending between the bus element and the terminal. The method includes applying a carrier element to the lead frame to form a laminate with the branches adhering to a first surface of the carrier element, and severing the branches from the bus element, leaving the branches mechanically connected to one another by the carrier element so as to form an in-process unit. The method also includes assembling a microelectronic element with the in-process unit so that the microelectronic element overlies a second surface of the carrier element.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.

Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m?/? and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. The first group of leads extends in a direction away from the second group of electrodes. Each of the second group of leads extends so as to pass between the first group of electrodes and is formed to be bent in the region between first and second straight lines.

Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.

Abstract: The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the preferred embodiments includes common leads coupled to an island, and a part of the common leads projects out from a resin seal body. The projecting common leads have a coupling portion. When mounting the semiconductor device, the common leads are bridged with brazing material. Thus, the heat generated by an integrated circuit chip mounted on the island is dissipated through the common leads to the outside of the resin seal body. In the preferred embodiments of the invention, a further improvement in heat dissipation characteristics can be accomplished by increasing the surface areas of the common leads.

Abstract: In order to mount a semiconductor element of a small electrode pitch, an inner lead portion of a lead frame is made thin and narrow to reduce a pitch. Even a semiconductor element in which an electrode arrangement pitch is smaller than conventionally can be mounted by flip chip bonding, the number of components such as a wire is reduced, and a possibility of wire cutting or the like caused by vibration or the like during semiconductor device assembling is reduced. A fine inner lead formation scheduled area of a conductor plate is half-etched to make a plate thickness smaller than that in a peripheral area. Then, the fine inner lead formation scheduled area is patterned to form a fine inner lead portion 22. Especially, a width of a tip 22a of the fine inner lead portion 22 is set smaller than those of a middle inner lead portion 23 and an outer lead portion 25.

Abstract: A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: A semiconductor device includes a substrate on which are formed a first group and a second group of leads; and a semiconductor chip having a first group and a second group of electrodes, the first group and a second group of electrodes being arranged respectively on both sides of a region between first and second straight lines, the first and second straight lines being parallel to each other. The semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. Each of the second group of leads has a bent portion, the bent portion being formed so that a contour of an inner side of each bend of the bent portion draws a curve.

Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.

Abstract: A plurality of leads includes a plurality of lead groups, each of which are formed of at least two first leads, and a plurality of second leads. Each of the second leads is positioned between an adjacent pair of the lead groups. Each of an outermost pair of the first leads of each of the lead groups includes a first portion and a second portion, the first portion of each of the outermost pair of the first leads being positioned at a first spacing apart and the second portion of each of the outermost pair of the first leads being positioned at a second spacing apart which is smaller than the first spacing. Each of the second leads is disposed in a manner to avoid a region that is sandwiched between the first portion of each of the adjacent pair of the lead groups and has a portion that is disposed in a region that is sandwiched between the second portion of each of the adjacent pair of the lead groups.

Abstract: A semiconductor package which includes a die pad that is exposed through the top surface of its molded housing, a semiconductor die having one power electrode electrically and mechanically connected to the underside of the die pad, and another power electrode electrically connected to a lead.

Abstract: Systems and methods are disclosed to dissipate heat from a semiconductor substrate. A package for integrated circuit includes a chip having a plurality of chip pads adapted to receive the variety of signals from or to output the same to an external circuit; a lead frame having a plurality of contact points each corresponding to a chip pad; and nano ceramic material in thermal communication with the chip for removing heat from the chip.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: The invention relates to a method for producing an electrical leadframe (10), in particular for a light-emitting diode component, having at least one first electrical connection conductor (2) and at least one second electrical connection conductor (3). The method includes a) production of a layer composite comprising an electrically insulating carrier layer (101) and an electrically conductive connection conductor layer (102), b) patterning of the carrier layer (101) in such a way that at least one contact-making window (7) toward the connection conductor layer (102) is produced in said carrier layer, and c) patterning of the connection conductor layer (102), in such a way that the first electrical connection conductor (2) and the second electrical connection conductor (3) are produced, at least one of which can be electrically connected through the contact-making window (7).

Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

Abstract: A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.

Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.

Abstract: A method of manufacturing a semiconductor device involves mounting a semiconductor chip, formed on top with a main electrode and a subelectrode smaller in area than the main electrode, on a die pad of an external lead frame through a first bonding material, mounting an inner lead frame in which plural inner leads for connecting the main electrode and the subelectrode on the chip to corresponding connecting pads of the external lead frame are joined together by a tie bar on the chip and the external lead frame through a second bonding material, heating the first and second bonding materials simultaneously for electrically connecting and fixing the chip to the die pad and the inner leads to the electrodes on the chip and the connecting pads of the external lead frame, and cutting the tie bar to separate the inner lead frame into the plural inner leads.

Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.

Abstract: A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.

Abstract: A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.