Layered Patents (Class 257/736)
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Method for generating layout pattern of semiconductor device and layout pattern generating apparatus
Patent number: 8312397Abstract: In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.Type: GrantFiled: September 2, 2009Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventor: Tomoyuki Inoue -
Patent number: 8304903Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.Type: GrantFiled: December 13, 2010Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Juan A Herbsommer, George J Przybylek, Osvaldo J Lopez
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Patent number: 8288178Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.Type: GrantFiled: August 6, 2009Date of Patent: October 16, 2012Assignee: Renesas Electronics CorporationInventor: Yoshinari Fukumoto
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Patent number: 8253027Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.Type: GrantFiled: February 24, 2010Date of Patent: August 28, 2012Assignee: Kyocera CorporationInventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
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Patent number: 8237270Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.Type: GrantFiled: February 24, 2011Date of Patent: August 7, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiro Kobayashi, Junichi Nakamura, Kentaro Kaneko
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Patent number: 8232639Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.Type: GrantFiled: November 23, 2010Date of Patent: July 31, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshio Kobayashi, Takaharu Yamano, Takashi Kurihara
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Patent number: 8193636Abstract: A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.Type: GrantFiled: March 10, 2008Date of Patent: June 5, 2012Assignee: Megica CorporationInventors: Jin-Yuan Lee, Hsin-Jung Lo
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Patent number: 8178957Abstract: A method of manufacturing an electronic component device, includes the steps of preparing a wiring substrate, which includes a silicon substrate, a concave portion provided on its upper surface side, a through hole formed to penetrate the silicon substrate on a bottom surface side of the concave portion, an insulating layer formed on the silicon substrate, a penetration electrode constructed by a lower conductor portion formed to a halfway position of a height direction from a bottom portion of the through hole and a connection metal member (indium layer) formed on the lower conductor portion in the through hole, and an electronic component having a terminal metal member (gold bump) on a lower surface side, and softening the connection metal member of the wiring substrate in a heating atmosphere and then sticking the terminal metal member of the electronic component into the connection metal member and connecting thereto.Type: GrantFiled: February 11, 2010Date of Patent: May 15, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Akinori Shiraishi, Mitsutoshi Higashi, Kei Murayama
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Patent number: 8148823Abstract: A package for one or more semiconductor die is described. A generally rectangular package includes two large terminals that occupy substantially the entire length of the package and provide low resistance connections. Additional connections may be provided preferably in a central portion of a short end of the package. BGA connections between the semiconductor die and the package substrate provide low impedance connections between the die and the package contacts. The package and connections facilitate current flow orthogonal to the longest package dimension maximizing conductor width and minimizing interconnection resistance.Type: GrantFiled: December 14, 2009Date of Patent: April 3, 2012Assignee: Picor CorporationInventors: Patrizio Vinciarelli, Claudio Tuozzolo
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Patent number: 8124449Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.Type: GrantFiled: December 2, 2008Date of Patent: February 28, 2012Assignee: Infineon Technologies AGInventors: Georg Meyer-Berg, Andreas Schloegl
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Patent number: 8106513Abstract: A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; a first capping layer on the top surface of the wire and the top surface of the dielectric layer; and a second capping layer on a top surface of the first capping layer.Type: GrantFiled: November 9, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
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Patent number: 8102052Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.Type: GrantFiled: February 14, 2011Date of Patent: January 24, 2012Assignee: Infineon Technologies AGInventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
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Patent number: 8089147Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.Type: GrantFiled: November 2, 2006Date of Patent: January 3, 2012Assignee: International Rectifier CorporationInventors: Mark Pavier, David Bushnell
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Patent number: 8084848Abstract: A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads, a first power lead arranged between the pair of first and second differential signal leads, a second power lead arranged between the pair of second and third differential signal leads, and a third power lead between which and the second power lead is the pair of third differential signal leads. A voltage provided by the first power lead is less than a voltage provided by the second power lead, and the voltage provided by the second power lead is substantially equal to a voltage provided by the third power lead.Type: GrantFiled: September 24, 2009Date of Patent: December 27, 2011Assignee: VIA Technologies, Inc.Inventor: Sheng-Yuan Lee
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Patent number: 8013441Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.Type: GrantFiled: October 16, 2006Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
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Patent number: 7993979Abstract: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.Type: GrantFiled: December 26, 2007Date of Patent: August 9, 2011Assignee: Stats Chippac Ltd.Inventors: Byung Tai Do, Linda Pei Ee Chua, Heap Hoe Kuan
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Patent number: 7981698Abstract: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.Type: GrantFiled: March 9, 2007Date of Patent: July 19, 2011Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Dariusz R. Pryputniewicz, Thomas F. Marinis, Gary B. Tepolt
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Patent number: 7982310Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.Type: GrantFiled: September 29, 2009Date of Patent: July 19, 2011Assignee: Seiko Epson CorporationInventor: Haruki Ito
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Patent number: 7968921Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.Type: GrantFiled: March 27, 2009Date of Patent: June 28, 2011Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
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Patent number: 7956462Abstract: A semiconductor device having a multilayer wiring structure and a manufacturing method thereof are provided. A semiconductor device and a manufacturing method thereof are provided in which the reliability and the manufacturing yield are high and the design constraint is small. Wirings are formed on a substrate. Low dielectric constant films are formed around the wirings. Reinforcement insulating films are formed in a dielectric material of a larger elastic modulus than that of a formation material of the low dielectric constant films and are arranged to overlap with the wirings when viewed perpendicularly to a substrate surface. Reinforcement insulating films are arranged to intersect with the wirings.Type: GrantFiled: February 15, 2008Date of Patent: June 7, 2011Assignee: Fujitsu LimitedInventors: Takashi Suzuki, Kiyoshi Ozawa
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Patent number: 7951709Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.Type: GrantFiled: September 10, 2010Date of Patent: May 31, 2011Assignee: Micron Technology, Inc.Inventor: David Pratt
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Patent number: 7951302Abstract: A method for forming a bump of a probe card is disclosed. In accordance with the method, a bump having a high aspect ratio for supporting a probe tip and a probe beam is formed using a semiconductor substrate as a mold eliminating a need for a photoresist film.Type: GrantFiled: August 2, 2007Date of Patent: May 31, 2011Assignee: Will Technology Co., LtdInventors: Bong Hwan Kim, Jong Bok Kim
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Patent number: 7944026Abstract: A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.Type: GrantFiled: December 21, 2007Date of Patent: May 17, 2011Assignee: Elpida Memory, Inc.Inventors: Kazutaka Koshiishi, Mitsuaki Katagiri, Satoshi Isa, Haruo Akahoshi
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Patent number: 7915088Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.Type: GrantFiled: April 8, 2008Date of Patent: March 29, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiro Kobayashi, Junichi Nakamura, Kentaro Kaneko
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Patent number: 7906840Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.Type: GrantFiled: September 4, 2008Date of Patent: March 15, 2011Assignees: Kyocera Corporation, Oki Electric Industry Co., Ltd., Kabushiki Kaisha Toshiba, Fuji Xerox Co., Ltd., Fujitsu Microelectronics Limited, Renesas Technology Corp., Ibiden Co., Ltd., Kanji Otsuka, Yutaka AkiyamaInventors: Kanji Otsuka, Yutaka Akiyama
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Patent number: 7898082Abstract: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.Type: GrantFiled: May 30, 2007Date of Patent: March 1, 2011Assignee: Infineon Technologies AGInventor: Bum Ki Moon
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Patent number: 7863737Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.Type: GrantFiled: April 1, 2006Date of Patent: January 4, 2011Assignee: Stats Chippac Ltd.Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
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Patent number: 7863729Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.Type: GrantFiled: April 21, 2009Date of Patent: January 4, 2011Assignee: Unimicron Technology Corp.Inventors: Shih Ping Hsu, Chung Cheng Lien, Shang Wei Chen
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Patent number: 7858438Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.Type: GrantFiled: June 13, 2007Date of Patent: December 28, 2010Assignee: Himax Technologies LimitedInventors: Chien-Ru Chen, Ying-Lieh Chen
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Patent number: 7855460Abstract: An electronic component is provided with a first conductor, an insulator for covering a surface of the first conductor, a via hole penetrating the insulator, and a second conductor located on a surface of the insulator and electrically connected to the first conductor through the via hole, and includes a shielding film having conductivity, being interposed between the first conductor and the second conductor, and covering an interface between the first conductor and the insulator in the via hole by extending continuously at least from the surface of the first conductor constituting a bottom surface of the via hole to an inner wall surface of the via hole.Type: GrantFiled: April 9, 2008Date of Patent: December 21, 2010Assignee: TDK CorporationInventor: Hajime Kuwajima
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Patent number: 7851910Abstract: The invention relates to a process for the multi-stage production of diffusion-soldered joints for power components with semiconductor chips, the melting points of diffusion-soldering alloys and diffusion-soldered joints being staggered in such a manner that a first melting point of the first diffusion-soldering alloy is lower than a second melting point of the second diffusion-soldering alloy, and the second melting point being lower than a third melting point of a first diffusion-soldered joint of the first diffusion-soldering alloy.Type: GrantFiled: March 31, 2004Date of Patent: December 14, 2010Assignee: Infineon Technologies AGInventor: Edmund Riedl
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Patent number: 7842889Abstract: The present invention is characterized by a structure having a substrate 1, and metallization layers 2 formed on the substrate 1, on which a Sn solder film 3 and an Ag film 4 are formed. The Ag film 4 is a metal free from oxidization at room temperature in the atmosphere. In a wet process, since only an exposed side of the Sn solder film 3 is oxidized by the cell reaction of Ag and Sn, an upper surface of the Ag film 4 on the solder film, which would otherwise affect the connection, is not oxidized. Since the Ag film 4 melts into the Sn solder simultaneously with melting of the Sn solder film 3, the Ag film 4 does not hinder the connection.Type: GrantFiled: January 13, 2009Date of Patent: November 30, 2010Assignee: Hitachi Kyowa Engineering Co., Ltd.Inventors: Shohei Hata, Naoki Matsushima, Takeru Fujinaga
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Publication number: 20100230808Abstract: The present invention relates to a semiconductor component that has a substrate and a projecting electrode. The projecting electrode has a substrate face, which faces the substrate and which comprises a first substrate-face section separated from the substrate by a gap. The gap allows a stress-compensating deformation of the projecting electrode relative to the substrate. The substrate face of the projecting electrode further comprises a second substrate-face section, which is in fixed mechanical and electrical connection with the substrate. Due to a smaller footprint of mechanical connection between the projecting electrode and the substrate, the projecting electrode can comply in three dimensions to mechanical stress exerted, without passing the same amount of stress on to the substrate, or to an external substrate in an assembly. This results in an improved lifetime of an assembly, in which the semiconductor component is connected to an external substrate by the projecting electrode.Type: ApplicationFiled: August 13, 2007Publication date: September 16, 2010Applicant: NXP, B.V.Inventor: Jasper Joerg
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Patent number: 7783142Abstract: Consistent with the present disclosure, a package is provided in which the PLC substrate, for example, is bonded to the underyling carrier though a limited contact area. The rest of the substrate is detached from the carrier so that stresses are applied to a limited portion of the PLC substrate. The PLC itself, however, is provided over that portion of the substrate that is detached from the carrier, and thus experiences reduced stress. Accordingly, high modulus adhesives, as well as solders, may be used to bond the PLC substrate to the carrier, thereby resulting in a more robust mechanical structure.Type: GrantFiled: December 24, 2008Date of Patent: August 24, 2010Assignee: Infinera CorporationInventor: Joseph Edward Riska
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Patent number: 7781886Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.Type: GrantFiled: January 10, 2006Date of Patent: August 24, 2010Inventors: John Trezza, John Callahan, Gregory Dudoff
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Patent number: 7737554Abstract: An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.Type: GrantFiled: June 25, 2007Date of Patent: June 15, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jeffrey Junhao Xu
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Patent number: 7659620Abstract: An integrated circuit package includes a flexible laminar substrate 1. The substrate 1 has a flexible layer 5 of heat conductive material on one of its faces. The layer 5 extends across an aperture 9 in the flexible substrate 1. A first integrated circuit 11 is mounted on the layer 5 within the aperture 9, and wire bonded to the substrate 1. A flip chip 21 is mounted on the first integrated circuit 11. The two integrated circuits 11, 21 are embedded in a resin body 23.Type: GrantFiled: November 28, 2005Date of Patent: February 9, 2010Assignee: Infineon Technologies, AGInventor: Elstan Anthony Fernandez
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Patent number: 7659619Abstract: A device includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors proximate to the first surface. The first semiconductor die is configured to have a flexibility compliance greater than a first pre-determined value in a direction substantially perpendicular to a plane including the plurality of proximity connectors in order to reduce misalignment in the direction between the plurality of proximity connectors and additional proximity connectors on another device.Type: GrantFiled: October 12, 2005Date of Patent: February 9, 2010Assignee: Sun Microsystems, Inc.Inventors: Arthur R. Zingher, Robert J. Moffat, Ronald Ho
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Patent number: 7656033Abstract: A semiconductor device using lead technology includes a semiconductor chip with external side electrodes of semiconductor components disposed on its top side. On its rear side, the semiconductor chip is connected to a rear side internal lead adapted to the rear side of semiconductor chip. On its top side, the semiconductor chip is connected a plurality of top side internal leads. The top side internal leads are electrically connected to external leads of the semiconductor device.Type: GrantFiled: February 26, 2007Date of Patent: February 2, 2010Assignee: Infineon Technologies AGInventors: Alexander Koenigsberger, Klaus Schiess
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Patent number: 7626264Abstract: A substrate for device bonding is provided, which enables bonding of a device with high bond strength to an Au electrode formed on a substrate such as aluminum nitride by soldering the device at a low temperature using a soft solder metal having a low melting point such as an Au—Sn-based solder having an Au content of 10% by weight. The substrate for device bonding comprises a substrate having an Au electrode layer formed on its surface and in which (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni and (iv) a solder layer composed of a solder containing Sn or In as a main component are laminated in this order on the Au electrode layer.Type: GrantFiled: March 24, 2005Date of Patent: December 1, 2009Assignee: Tokuyama CorporationInventor: Hiroki Yokoyama
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Patent number: 7615864Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.Type: GrantFiled: December 17, 2004Date of Patent: November 10, 2009Assignee: Seiko Epson CorporationInventor: Haruki Ito
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Patent number: 7605683Abstract: In a monolithic electronic component in which a resistive element is incorporated by forming a resistor film on a terminal electrode, a plating film can be formed on the terminal electrode having the resistor film via electroplating in an efficient manner and with a uniform film thickness. In order to form the terminal electrode, the resistor film is disposed directly on the surface of the component body, and a conductive resin film having a relatively low volume resistivity is disposed over the resistor film. The conductive resin film is preferably adapted to have a specific resistance of less than about 1×10?4 ?·m, on which a plating film having a uniform film thickness can be formed efficiently via electroplating.Type: GrantFiled: February 12, 2008Date of Patent: October 20, 2009Assignee: Murata Manufacturing Co., Ltd.Inventors: Takashi Sawada, Kenjiro Hadano
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Patent number: 7535107Abstract: A method is described for combining the diverse strengths of two materials in a tiled film construction. The first material provides a foundation of intersecting grid lines on a substrate and the second material is contained within the grid lines and has a valued property for a particular application. In a preferred embodiment, a tiled dielectric layer has improved low-k dielectric performance while avoiding film stress problems that can lead to delamination or cracking. CTE mismatch is overcome at the cost of an additional masking step. This tiling method and layered binary construction enable Cytop to be used as a high performance low-k dielectric on most substrates including semiconductor wafers and copper panels or foils.Type: GrantFiled: October 12, 2005Date of Patent: May 19, 2009Assignee: Salmon Technologies, LLCInventor: Peter C. Salmon
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Patent number: 7531897Abstract: A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a second height smaller than said first height. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.Type: GrantFiled: January 29, 2002Date of Patent: May 12, 2009Assignee: STMicroelectronics S.r.l.Inventor: Ubaldo Mastromatteo
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Patent number: 7522405Abstract: A method and system are disclosed for a high current electrical switch. The switch may be suitable for switching, rectifying or blocking direct current in the range of one to a thousand amperes per module or assembly. It does so with such high efficiency that it produces relatively insignificant heat; such that it requires little or no cooling by convection or radiation. The relatively low heat that is generated in the process is conducted away quite effectively by the electric cables connected to the device.Type: GrantFiled: May 23, 2005Date of Patent: April 21, 2009Assignee: Perfect Switch, LLCInventor: H. Frank Fogleman
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Patent number: 7518242Abstract: A semiconductor device has a bonding pad configured to be bonded to a bonding member, a test pad configured to contact with a test probe at a test, and an internal circuit electrically connected to the bonding pad and the test pad. The bonding pad overlaps with the internal circuit in a direction vertical to a surface of a semiconductor chip. The test pad does not overlap with the internal circuit in the direction.Type: GrantFiled: November 24, 2004Date of Patent: April 14, 2009Assignee: NEC Electronics CorporationInventor: Miho Hirai
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Patent number: 7514350Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which a pad is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; a metal layer formed on the pad, the metal layer being less oxidizable than the pad; an insulating section formed of resin adjacent to the chip component; and an interconnect which is formed to extend from above the metal layer, over the insulating section and to above the interconnect pattern.Type: GrantFiled: March 1, 2004Date of Patent: April 7, 2009Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 7485976Abstract: A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux(122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.Type: GrantFiled: December 15, 2003Date of Patent: February 3, 2009Assignee: NXP B.V.Inventor: Carl Knudsen
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Patent number: 7485958Abstract: A device with a beam structure includes a substrate, an anchor and a cavity which are provided on and over the substrate, respectively, and a beam structure which is provided on the anchor and over the cavity, extends in a first direction and includes a plurality of convex portions and a plurality of concave portions, each of the convex portions having such a stress gradient as to provide a convex warp, and each of the concave portions having such a stress gradient as to provide a concave warp. The convex portions and the concave portions are alternately repeatedly arranged.Type: GrantFiled: May 23, 2006Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Tamio Ikehashi
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Patent number: 7482692Abstract: A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten plug and a lower metal line layer. The plug structure of a semiconductor device includes a silicon substrate in which various elements for the semiconductor device are formed, a first dielectric film formed on the silicon substrate, having a first contact hole, a first plug buried in the first contact hole of the first dielectric film, having a low aspect ratio, a second dielectric film formed on an entire surface including the first dielectric film, having a second contact hole on the first plug, a second plug buried in the second contact hole of the second dielectric film, having a low aspect ratio, and a metal line formed on the second plug.Type: GrantFiled: December 30, 2005Date of Patent: January 27, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: In Kyu Chun