Abstract: Plastic ball grid array (PBGA) packages comprised of organic carriers on which are mounted and encapsulated semiconductor chips, providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A semiconductor device including a semiconductor element mounted on a first surface of a wiring substrate, and a plurality of conductive land portions formed and exposed at a second surface of the wiring substrate which is opposite to the first surface. A plurality of solder balls are respectively joined to the plurality of conductive land portions. A plurality of reinforcement resin film portions are formed to reinforce coupling between the solder balls and the conductive land portions. Each of the reinforcement resin film portions is formed around a portion of the solder ball joining to the conductive land portion. Each of the reinforcement resin film portions being bent to form a portion along the wiring substrate and a portion along the side surface of the solder ball. The coupling between the solder balls and the conductive land portions is reinforced by elastic force of the bent portions of the reinforcement resin film portions.

Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.

Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Abstract: A method of producing layered metal components is described which obviates the need for layering the terminals twice. The method includes the steps of providing a strip of base material, layering the base material with layering material, and cutting individual pieces from the strip such that the layering material is wiped across the surface of the base material which would otherwise be exposed by the separation.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern at the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns.

Abstract: A method of solder-coating a metallic pad provided on a substrate, whereby at least the surface of the pad is provided with a deposit of solder paste, which paste comprises a suspension of metallic solder particles which, when molten, have a surface energy lower than the critical surface energy of the metallic pad but higher than the critical surface energy of the substrate surface outside the borders of the pad, whereby application of heat causes metallic solder particles within the paste lying upon the pad to melt and fuse together into an essentially continuous metallic solder layer, whereas the metallic solder particles within any paste lying upon the substrate surface outside the borders of the pad do not thus fuse together into a layer but are instead deposited as mutually-isolated solder beads, which beads can be subsequently removed from the substrate surface after completion of the heating process.

Abstract: A semiconductor device includes at least one bump electrode for inputting and outputting signals to and from the semiconductor device. The bump electrode is positioned above a semiconductor substrate with an electrode pad and metal layer disposed therebetween. A resin film covers a surface of the semiconductor substrate except at a top area of the bump electrode. The bump electrode projects a sufficient distance above a top surface of the resin film so that heat induced defects are reduced and pressure exerted on a top area of the bump electrode is absorbed to suppress occurrence of cracks in the resin film.

Abstract: A method of making a semiconductor chip 1 having a first electrodes 11, 12 on main surface 1a thereof, a second electrode 13 made of a conductive resin electrode having a base portion 131 in contact with a surface 1b opposite to the main surface 1a of the semiconductor chip 1, and a side portion 132 extended from one end portion of the base portion 131 in the direction toward the main surface 1a of the semiconductor chip 1, wherein an end part of the side portion 132 of the second electrode 13 is exposed on the same side as the first electrodes 11, 12.

Abstract: A monolithically integrated, multi-layer device is fabricated with single crystal films of desired orientation grown from arrayed nucleation sites on amorphous and/or non-single crystal surfaces. Examples of devices which can be produced are CMOS and bipolar devices in single crystal (100) and (111) Si films on amorphous surfaces such as SiO2 or Si3N4 in processed ULSIC wafers. These devices can be integrated along the 3rd dimension. Thus, 3-dimensional IC's can be fabricated. Similarly, high performance CMOS devices in SiGe films, MESFET, HEMT and optical devices in compound semiconductor films, can be fabricated within processed ULSIC wafers. Further, Si—, GaAs—, and other compound semiconductor-based devices in the respective single crystal films with different orientations deposited selectively in a given level, and in multilevel IC's, can be manufactured.

Abstract: A semiconductor device has an interconnection pattern that crosses a vertical step. The part of the vertical step crossed by the interconnection pattern includes a horizontal side-step. The horizontal side-step increases the total length of the crossing, thereby reducing the risk of electrical discontinuity at the crossing, without increasing the width of the interconnection pattern itself.

Abstract: A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of many short segments rather than several long, straight sections, the subsequent chemical-mechanical polishing step does not cause significant cupping of the metal in the trench.

Abstract: A spherical semiconductor device includes a spherical semiconductor element having one or more electrodes on its surface. Spherical conductive bumps are formed at the positions of the electrodes. The electrodes are so arranged as to contact a common plane. Spherical bumps constituting a group to be connected to the outside protrude above the spherical semiconductor element such that a predetermined gap is formed between a plane or a spherical surface capable of contacting the spherical bumps and the surface of the spherical semiconductor element. The spherical semiconductor device is connected to various circuit boards or another semiconductor device through the spherical bumps. This affords easy and accurate electrical connections to the outside.

Abstract: A ball grid array package and its packaging process is described. A thermal dissipation substrate has a first surface and a second surface. An insulating layer and a copper foil are built up sequentially on the second surface. The copper foil is patterned to form multiple of conducting wire traces, and then a solder resist is coated on the surfaces of both the conducting wire traces and the insulating layer. Afterwards, part of the surfaces of the conducting wire traces is exposed to form multiple bonding fingers and multiple ball pads. Moreover, an aperture is formed at the center of the thermal dissipation substrate and insulating layer to penetrate through the thermal dissipation substrate and the insulating layer. Furthermore, a chip having its active surface bound to the first surface and has multiple bonding wires passing through the aperture to electrically connect the bonding pads to bonding fingers.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: A method of manufacturing a semiconductor package including the steps of adhering inner leads to a semiconductor chip surface via an insulating adhesive, forming an insulating layer on the semiconductor chip and upper surfaces of the inner leads such that bonding pads formed on the semiconductor chip and portions of the inner leads are exposed through an opening, forming a conductive layer in the opening to electrically connect the bonding pads to the inner leads, and forming a semiconductor package by molding the semiconductor chip, the inner leads, the insulating layer, and the conductive layer with a molding material.

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metalplugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract: There is provided an I/O pin by which an MCM is positively prevented from being damaged by solder flowing from the fore end to the base of the I/O pin when the I/O pin is soldered in the case of mounting the MCM. An I/O pin used for an electrical connection is provided, one end of which is perpendicularly fixed to an MCM and the other end of which is soldered to a predetermined position on the mother board in the case of mounting the MCM on the mother board. In an intermediate portion of the I/O pin, there is formed a solder dam composed of a plated layer of Ni of low solder wettability, a layer of highly heat-resistant resin or a layer of high-temperature solder.

Abstract: An electronic component comprises an insulator substrate (11), a layered member composed of a plurality of insulator resin layers (12a-12f) and a plurality of conductor pattern layers (13a-13f) alternately stacked on the insulator substrate to form a first conductor line and a second conductor line each of which comprises at least one conductor layer, first and second external electrode terminal portions connected to opposite ends of the first conductor line and covering first and second areas of side surfaces of said layered member and the insulator substrate, respectively, and a third external electrode terminal portion connected to one end of the second conductor line and covering a third area of the side surfaces of the layered member and the insulator substrate. The second conductor lines have magnetic and electrocapacitive coupling with respect to the first conductor line.

Abstract: A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

Abstract: In a semiconductor device 1 according to the present invention, a plurality of inner leads are bonded to a front surface of a semiconductor element 11 covered by a package 10, with bent portions 17 formed at some inner leads 13a among the plurality of inner leads 13 and the front ends of the bent portions 17 exposed at a front surface of the package 10. This structure ensures that the semiconductor element is not caused to move vertically inside the forming die by the pressure of the liquid resin or the like during the sealing process.

Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.

Abstract: A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 through the medium of a conductive adhesive. Further, it will be able to mount an electronic part to an element to be mounted by utilizing a conductive adhesive forming an external electrode 3 as a connecting element.

Abstract: Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.

Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Abstract: A lead frame for semiconductor devices including a metal substrate having inner leads and outer leads, a nickel thin layer formed on the metal substrate, an outer layer formed of palladium or a palladium alloy on the nickel thin layer, and a protection layer formed of gold or platinum between the nickel thin layer and the outer layer.

Abstract: A surface mount area-array integrated circuit package is disclosed. The package consists of a package substrate having conductive vias and internal and external conductive traces, a semiconductor die electrically and mechanically connected to the top surface of package substrate, an area-array of conductive surface mount terminations electrically and mechanically connected to the bottom of the package substrate, and at least one adhesive mass. The at least one adhesive mass is located on the bottom of the package substrate and replaces the conductive terminations in the area(s) where the joint strain energy density is calculated to be the greatest. When mounted on a substrate, the at least one adhesive mass adheres the package to the substrate. Increased mechanical and electrical reliability is thus achieved.

Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.

Abstract: A method of inspecting a chip with projecting electrodes or bumps, part of which are lacking, includes arranging electrode terminals for detecting projecting electrodes along four corners of a peripheral edge of a rectangular semiconductor chip, measuring an electrical characteristic of each of the electrode terminals, and determining the semiconductor chip as a defective one in terms of projecting electrodes if the measured result does not conform to a desired characteristic. As another feature, the surface of the projecting electrode of the electrode terminal is flattened.

Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surfaces wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: An electronic device includes one or more semiconductor chips interconnected to a next level substrate in a flip chip mode using flexible conductive adhesive having a low modulus of elasticity. The flexible conductive adhesive is applied as conductive bumps on the contact pads of the substrate or on the contact pads of the semiconductor chips and is a flexible thermoplastic or thermosetting resin filled with electrically-conductive particles. Other electronic devices, such as packaged components including resistors, capacitors and the like, are bonded with the same flexible conductive adhesive bump approach as is employed for the semiconductor chips. The contact pads of both the chip and the next level substrate are preferably passivated with a metallic coating, preferably a precious metal, prior to interconnection to inhibit oxidation of the pads.

Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Abstract: A vertical interconnect package for electronic components and a method to manufacture same.The invention provides a tripartite lead frame-based Vertical Interconnect Package (VIP) which provides integrated feedthrough and integrated shielding in a non-ceramic package. One frame functions as the substrate for coupling the IC device, the second lead frame and third lead frames form shielding and feedthroughs, with the third also providing a lid whereby an airtight chamber around the IC is formed. The invention provides a ground button (the shortest path to the die) divided into n sections providing additional RF and separate ground paths; lead frame connections are used for DC. A method for assembling includes batch lead frame assembly and test prior to singulation.The VIP provides improved performance at lower manufacturing cost and provides easy interfaces to the printed circuit board in surface mount technology manufacturing and is compatible with die mount technologies such as flip-chip.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

Abstract: A multi-layer lead frame for use in a semiconductor package is described. The described lead frame is particularly well suited for application where fine pitch leads and/or lead multi-routing capability is required. In one embodiment, the multi-layered lead frame includes a first lead trace layer superimposed over and adhered to a second lead trace layer. The first and second lead trace layers each have a plurality of leads and each layer has an external portion and an internal portion. Each of the leads in the first trace layer has an associated lead in the second trace layer that has a matching external portion. The matching external portions are bonded together when the trace layers are superimposed. At least some of the leads in the first trace layer have different lengths than the matching leads of the second trace layer. This permit the leads to be routed separately, and may be used to facilitate finer lead pitches than would be possible in full thickness lead frames.

Abstract: A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound characteristic, and solderability. The leadframe includes a base structure made from a conductive material. A silver plating is formed over the base structure of the leadframe, and a palladium plating is formed over the silver plating. Depending on actual requirements, a copper layer and a nickel plating can be formed between the silver plating and the base structure of the leadframe, and a palladium/nickel plating can be formed between the silver and palladium platings. Further, a gold layer can be formed over the palladium plating. The palladium plating and the palladium/nickel plating can be formed all over the leadframe or selectively formed only in the external-lead area of the leadframe.

Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: Thermal heater chip (1) is located within an opening of TAB circuit tape (5) and the TAB leads (3) are welded to the chip. This assembly is turned so that the underside of the leads face upward, and a curable, electrically insulative liquid is applied and cured to form a solid (11). The bottom of the chip is then attached to a heat radiating support (7) using heat conductive adhesive. The cured solid on the leads prevents any adhesive reaching the leads from causing an electrical shunt. The resulting printhead dissipates excess heat from the chip well from the support.

Abstract: There is provided a leadframe assembly for encapsulation in a polymer resin which prevents post-assembly fracture or swelling of the resin. The leadframe is coated with an adhesion enhancing layer that increases the shear stress required for delamination to in excess of about 3.4 MPa. In combination with this adhesion enhancing layer is a compliant die attach adhesive bonding an integrated circuit device to a central die attach paddle. This compliant die attach adhesive has a compliancy factor, E.multidot.a of less than 1.5 MPa/.degree.C. and a thickness of from about 0.01 mm to about 0.08 mm.

Abstract: A ball grid array semiconductor package including a semiconductor chip, at least one lead having one end attached to the semiconductor chip and other end bent at a predetermined angle, a wire connecting the bent lead to an electrode formed on the semiconductor chip, a first bump attached to a bent end portion of the bent lead, and a resin molding enclosing the semiconductor chip, the lead and the wire to allow one side surface of the bump to be exposed out of the resin molding.

Abstract: First and second electrically insulating substrates are joined with each other at respective joining faces thereof. Each of the first and second insulating substrates has an annular groove at the joining face, and a plurality of through holes along outer and inner peripheries of the annular groove. An annular core is mounted in the annular groove. A cylindrical connection is formed in each through hole, and a radial connection is formed on an outer surface of each insulating substrate so as to connect opposite cylindrical connections. A toroidal coil is formed by serially connecting cylindrical connections and radial connections. An IC chip is mounted on the outer surface of the first insulating substrate, and connected to the toroidal coil and electronic part. The toroidal coil and the electronic part are coated with an electrically insulating material.

Abstract: Chip-support arrangement (23) with a chip support (23) for the manufacture of a chip casing, said chip support being provided on a support foil (20) with conducting paths (21) which are connected on the front side of the support foil facing a chip (39) to contact-surface metallizations (40) of the chip and which with their free ends form a connection-surface arrangement (42) distributed in planar manner for the purpose of connection to an electronic component or a substrate, whereby the conducting paths (21) are arranged on the reverse side of the support foil (20), recesses (28) in the support foil (20) are provided in the region of the contact-surface metallizations (40), the conducting paths for forming the connection-surface arrangement (42) are covered with a perforated mask (36) and the thickness (s) of the support foil is smaller than or substantially equal to the height (h) of the contact-surface metallizations (40) on the surface of the chip.

Abstract: Leaded substrates carriers and packaged integrated circuit devices that utilize such carriers as well as method of manufacturing the same are disclosed. The substrate carrier comprises a series of conductor lines for electrically connecting the active side of the chip to leads formed as part of the substrate carrier and extending from the side of the substrate carrier. The leads extend beyond the sides of the substrate carrier and have planar metal surfaces designed to allow surface mounting and testing of the assembly.

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.