Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Abstract: A bonding method of a flexible film is provided, which includes: positioning an anisotropic conductive film on a plurality of first signal lines formed on the flexible film to be bonded to a thin film transistor (TFT) panel; arranging the anisotropic conductive film on the TFT panel to align the first signal lines formed on the flexible film and a plurality of second signal lines formed on the TFT panel; positioning at least one portion of a protection film for protecting the second signal lines of the flexible film to be overlapped with the TFT panel; and pressing the flexible film and the TFT panel.

Abstract: A semiconductor device includes a semiconductor substrate, an electrode pad electrically connected to a circuit element formed on the semiconductor substrate, a connection wiring electrically connected to the electrode pad and extending on the semiconductor substrate, and a post electrode formed on the connection wiring. The semiconductor device further includes an adhesion film formed on the side surface of the post electrode, and a sealing layer that has light-shielding property and seals the surface of the adhesion film and the connection wiring.

Abstract: The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads on the circuit carrier. The conductor tracks include an electrically conductive polymer in the semiconductor device.

Abstract: According to the invention, a layer made of an electrically insulating material is applied to a substrate and a component that is arranged thereupon in such way that said layer follows the surface contour formed by the substrate and the component.

Abstract: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: In a method according to the present invention, a substrate thinning process is performed on a bumped substrate prior to the ultimate solder reflow process to heal bump defects caused by the substrate thinning process. Concurrently, the risk of substrate breakage is reduced compared to the prior art process since the number of process steps, requiring handling of thinned substrates, is reduced.

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: The invention includes a first step for forming a first conductive layer composed of a high melting point metal to be in contact with an insulating layer; and a second step for forming a second conductive layer by discharging a composition containing a conductive material so as to be in contact with the first conductive layer. The first conductive layer is formed prior to forming the second conductive layer by droplet discharging, and hence, adhesiveness and peel resistance of the second conductive layer are improved. Furthermore, the insulating layer is covered with the first conductive layer, thereby preventing damage or destruction of the insulating layer.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: In a lead-frame configuration (60), a module (70) and a data carrier (72), two connecting plates (12, 13) of the module (70), which are each intended for connection to a connecting contact or bump (47, 48) of a chip (41), are connected to a reinforcement film (66, 71) formed from a fiber-reinforced film of plastics material by means of a layer (73) of an adhesive that is particularly well suited to transmitting shear forces, in which case there is additionally provided in an advantageous further embodiment, on the reinforcement film (66, 71), at least one further layer (74, 75, 76) that is able to serve for protecting, damping or fastening purposes.

Abstract: Arrangements are used for minimizing signal path discontinuities.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.

Abstract: An electronic module includes electronic circuitry and first and second connection mechanisms, both operationally connected to the electronic circuitry, for mounting the module in a larger electronic device by different respective methods. Preferably, the first connection mechanism is a robotic connection mechanism such as a BGA with one or more solder balls and the second connection mechanism is a manual connection mechanism such as a plug with one or more electrically conducting pads, both mechanisms being for mounting the module on a PCB.

Abstract: A lead frame for a semiconductor package having not only high molding resin adhesiveness and a low delamination problem under a severe moisture absorbing atmosphere but also high interface adhesiveness and solder wettability of an Au wire, and a method of manufacturing the lead frame are provided. The lead frame includes a base metal layer formed of a metal and a plurality of plating layers having different components formed on at least a surface of the base metal layer, wherein the plating layers include, a Ni plating layer deposited on at least a surface of the base metal layer and formed of Ni or an Ni alloy, a Pd plating layer stacked on at least a surface of the Ni plating layer and formed of Pd or a Pd alloy, and a protection plating layer stacked on at least a surface of the Pd plating layer and formed of Au or an Au alloy, wherein the Ni plating layer is formed to have a predetermined a thickness and a surface coarseness.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to the integrated circuit. In one embodiment, the method includes forming an opening in the workpiece in alignment with the terminal. The opening can be a through-hole extending through the workpiece or a blind hole that extends only partially through the substrate. The method continues by constructing an electrically conductive interconnect in the workpiece by depositing a solder material into at least a portion of the opening and in electrical contact with the terminal. In embodiments that include forming a blind hole, the workpiece can be thinned either before or after forming the hole.

Abstract: The present invention provides a wafer structure having a plurality of bonding pad, an adhesion layer, a barrier layer, a wetting layer, a plurality of bump, a first passivation layer and a second passivation layer. The bonding pads are disposed on the active surface of the wafer and exposed by the first passivation layer. The second passivation layer is disposed on the first passivation layer and exposing the bonding pads. An adhesion layer is disposed on the bonding pad and covers a portion of the first passivation layer. The second passivation layer covers the first passivation layer and a portion of the adhesion layer. The barrier layer and the wetting layer are sequentially disposed on the adhesion layer and the bumps are disposed on the wetting layer.

Abstract: Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected directly with the ground trace.

Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.

Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).

Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Abstract: A semiconductor device is provided having: a board; a metallization pattern formed on the first face of the board; a first layer formed so as to not cover the first portion of the metallization pattern but to cover the second portion; and a semiconductor chip mounted on the first face of the board and electrically connected with the metallization pattern in the first portion. A resin portion is provided between the semiconductor chip and the board and from there onto the first portion of the metallization pattern outside the semiconductor chip so as to not reach a boundary between the first and second portions. A second layer is provided on the second face of the board so as to overlap the boundary of the metallization pattern and not overlap the resin portion.

Abstract: A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies include stamped and formed contacts having an insulative plastic molded over a central section of the contact. A grounding clip surrounds the housing and is conductively connected to the substrate, and has spring arms which are connectable to heat sink hardware on one side thereof and to a printed circuit board on the other side.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.

Abstract: An elongated bonding pad comprises two areas, a bonding area and an elongated probing area. The bonding area is located on the edge of an integrated circuit device for wire bonding. The elongated probing area is located on the inner area of the device. The long dimension of the elongated probing area is large enough for carrying a probing mark and the short dimension of the probing area is electrically and mechanically connected to the bonding area. Such elongated bonding pad can reduce the possibility of bonding wire open failures caused by wafer sort probing and increase the device's capacity of hosting more electrical components.

Abstract: The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

Abstract: A wiring board comprising: a wiring laminate portion including dielectric layers containing polymeric material and conductor layers laminated alternately so as to form a first main surface out of one of said dielectric layers; and a plurality of metal terminal pads disposed on said first main surface; wherein: each of said metal terminal pads has a structure in which a Cu-plated layer is disposed on a side of said first main surface and an Au-plated layer is disposed in an outermost surface layer portion of said metal terminal pad, while an electroless Ni-plated layer having a P content not higher than 3% by weight is disposed as a barrier metal layer between said Cu-plated layer and said Au-plated layer.

Abstract: A method for manufacturing a semiconductor package, the method including the steps of attaching a bottom surface of a semiconductor wafer to a first supporting member, forming a through hole in the semiconductor wafer, separating the semiconductor wafer from the first supporting member, forming an insulating layer on at least the bottom surface of the semiconductor wafer and the inner wall of the through hole, forming a conducting layer underneath the semiconductor wafer, the conducting layer spanning at least the bottom of the through hole; and forming a conductive member in the through hole and in electrical contact with the conducting layer.

Abstract: An interposer has a connection electrode formed on the insulating substrate surface, and a solder bump connects with the connection electrode. The insulating substrate surface is made rough where unevenness is formed, and the connection electrode peelable from the insulating substrate surface in a region with which the solder bump is connected by coating surface low active agent.

Abstract: A semiconductive chip having at least one active device, and at least one bond pad located on said active device. The bond pad has at least one deformable member, and the deformable member is deformable when conductive stud is bonded to said bond pad so as to prevent damage to the active device during the bonding of the conductive stud to the bond pad, such as by an ultrasonic bonding technique. A plurality of the deformable members may define a pattern on the bond pad that deforms when the conductive stud is bonded to the bond pad.

Abstract: A compact switching device for applications in integrated circuits is disclosed. The switching device comprises a P-type conductive channel and an N-type conductive channel, both formed on a very-thin semiconductor film. A lightly doped portion in each of said conductive channels is controlled by a single gate electrode formed on a dielectric layer above the channel regions. These lightly doped portions are designed to provide an enhanced conductive state by accumulating majority carriers at the surface, and a non-conductive state by fully depleting majority carriers from the entire thin-film thickness from the single gate electrode provided. Both gate electrodes are coupled to a common input, and both drain nodes are coupled to a common output. Design parameters are optimized to provide complementary devices side-by-side on a single geometry of the thin film, merged at the common drain node.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Abstract: A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Abstract: An electronic chip component includes a component body and a plurality of terminal electrodes disposed on outer surfaces of the component body. At least one of the terminal electrodes includes a cured resin film including dispersed conductive particles, an outer conductive film formed on the cured resin film by electroplating, and additional conductive metallic particles being dispersed on an interface between the cured resin film and the outer conductive film.

Abstract: A manufacturing method of a ball grid array package mainly comprises providing a carrier unit with an upper surface and a lower surface, mounting a plurality of solder balls on the lower surface of the carrier unit, disposing a protective layer below the lower surface to cover the solder balls, placing a chip on the upper surface of the carrier unit and electrically connecting the carrier and the chip, encapsulating the chip and removing the protective layer so as to form said ball grid array package.

Abstract: A submount can mount on it a semiconductor light-emitting device with high bonding strength, and a semiconductor unit incorporates the submount. The submount comprises (a) a submount substrate, (b) a solder layer formed at the top surface of the submount substrate, and (c) a solder intimate-contact layer that is formed between the submount substrate and the solder layer and that has a structure in which a transition element layer consisting mainly of at least one type of transition element and a precious metal layer consisting mainly of at least one type of precious metal are piled up. In the above structure, the transition element layer is formed at the submount-substrate side. The semiconductor unit is provided with a semiconductor light-emitting device mounted on the solder layer of the submount.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A semiconductor device to prevent breakage of a semiconductor chip is disclosed. The device incorporates a sealing member, a semiconductor chip and having a source and gate electrodes on a first main surface and a drain electrode on a second main surface, a first electrode plate having an upper surface exposed to an upper surface of the sealing member and a lower surface exposed to a lower surface of the sealing member, and second electrode plates each having a lower surface exposed to the lower surface of the sealing member. The drain electrode of the chip is electrically connected to the drain electrode plate through an adhesive. Stud type bump electrodes are formed by gold wire on the source and gate electrodes and are covered with an electrically conductive adhesive. The bump electrode(s) and the source and gate electrode plates are electrically connected with each other through the adhesive.

Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.

Abstract: A semiconductor device to be mounted on an external electronic device includes a film substrate on which wiring electrodes are formed, the wiring electrodes being partially covered with a covering member; and a semiconductor chip mounted on the film substrate. In this semiconductor device, the film substrate is folded so that at least one edge of the film substrate is on a side opposite to a side on which the semiconductor chip is mounted, and portions of the wiring electrodes exposed from the covering member on a surface of the film substrate on which the semiconductor chip is mounted are to be connected to electrodes of an external electronic device.

Abstract: An electronic device and a method for producing the electronic device which has at least one microscopically small contact area for an electronic circuit having interconnects that are on a surface of a substrate. A three-dimensionally extending microscopically small contact element is integrally one-piece connected to the contact area.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses two bare die field effect transistors whose input and output electrodes are solder attached to low resistance, high current posts in the package. An associated controller chip is mounted to a rigid circuit board, and the circuit board is mechanically attached to the posts. The circuit board thereby gives physical rigidity to the package, but carries no high currents. The use of low resistance, high current posts reduces the heat generated, improving the long term reliability.

Abstract: An electronic module contains a semiconductor chip that has flexible chip contacts. The flexible chip contacts are disposed on an uppermost metallization layer and have a dimensionally stable contact plate which is connected to contact surfaces on the uppermost metallization layer via electrically conductive components in an elastomeric embedding compound.

Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.

Abstract: The invention is intended for providing a semiconductor package structure which prevents degradation in characteristics of a semiconductor device, and breakage of interconnections, when the semiconductor device is packaged on a circuit substrate. In the package structure having the semiconductor device mounted on the circuit substrate, bump electrodes of the semiconductor device are placed on input/output terminal electrodes of the circuit substrate and are electrically and mechanically connected thereto by bonding with a conductive adhesive, and the semiconductor device is bonded and fixed to the circuit substrate by a resin film formed previously on a surface of a main body of the circuit substrate. The structure does no damage to a semiconductor functional part and to interconnections, and allows mounting with a lower load as compared to structures using conventional anisotropic conductive films and the like.

Abstract: The invention concerns a flexible substrate comprising an inner lead connected to an external connection terminal formed on a substrate, and a base film formed on the lead. The base film area above the substrate and closest to the terminal is thinner than the terminal. The invention also provides a semiconductor device comprising an inner lead connected to an external connection terminal formed on a substrate, and a base film formed on the lead. The base film area above the substrate and closest to the terminal is thinner than the terminal. The invention also provides for a manufacturing method a semiconductor device comprising a substrate, an external connection terminal, and an inner lead with a base film. Further, the invention provides a semiconductor device with a substrate with a chamfered corner between the connection and side faces. By the invention, connection of an inner lead or a flexible substrate is made easier.