Silicide Of Refractory Or Platinum Group Metal Patents (Class 257/757)
-
Patent number: 7061029Abstract: A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.Type: GrantFiled: February 24, 2005Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Wen-Fang Lee, Wei-Lun Hsu, Yu-Hsien Lin
-
Patent number: 7053462Abstract: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.Type: GrantFiled: December 4, 2002Date of Patent: May 30, 2006Assignee: Micron Technology, Inc.Inventors: Sam Yang, John M. Drynan
-
Patent number: 7026692Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.Type: GrantFiled: November 12, 2003Date of Patent: April 11, 2006Assignee: Xilinx, Inc.Inventor: Kevin T. Look
-
Patent number: 7009279Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.Type: GrantFiled: May 12, 2004Date of Patent: March 7, 2006Assignees: Hitachi, Ltd., Trecenti Technologies, Inc.Inventors: Shingo Nasu, Tomio Iwasaki, Hiroyuki Ohta, Yukihiro Kumagai, Shuji Ikeda
-
Patent number: 6984864Abstract: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.Type: GrantFiled: June 18, 2003Date of Patent: January 10, 2006Assignee: Renesas Technology Corp.Inventors: Tomoaki Uno, Yoshito Nakazawa
-
Patent number: 6960832Abstract: In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.Type: GrantFiled: January 22, 2004Date of Patent: November 1, 2005Assignee: Renesas Technology Corp.Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shuji Ikeda
-
Patent number: 6958541Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.Type: GrantFiled: July 25, 2003Date of Patent: October 25, 2005Assignee: LSI Logic CorporationInventors: Sean Erickson, Kevin Nunn, Norman Mause
-
Patent number: 6940172Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.Type: GrantFiled: August 28, 2001Date of Patent: September 6, 2005Assignee: Micron Technology, Inc.Inventors: Gurtej Singh Sandhu, Donald L. Westmoreland
-
Patent number: 6917112Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.Type: GrantFiled: August 26, 2002Date of Patent: July 12, 2005Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Gurtej Sandhu
-
Patent number: 6909154Abstract: Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of the top surface of a semiconductor device, annealing at least a portion of the device, and removing a substantial portion of the one or more sacrificial layers, where the removing results in no substantial physical alterations to the device.Type: GrantFiled: November 17, 2003Date of Patent: June 21, 2005Assignee: Intel CorporationInventors: Mark Y. Liu, Justin K. Brask
-
Patent number: 6906420Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.Type: GrantFiled: December 18, 2003Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takeshi Harada
-
Patent number: 6905922Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.Type: GrantFiled: October 3, 2003Date of Patent: June 14, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Yee-Chia Yeo
-
Patent number: 6885103Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.Type: GrantFiled: July 17, 2003Date of Patent: April 26, 2005Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Dong Kyun Sohn, Ji Soo Park, Jong Uk Bae
-
Patent number: 6858904Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.Type: GrantFiled: August 30, 2001Date of Patent: February 22, 2005Assignee: Micron Technology, Inc.Inventors: Ammar Derraa, Sujit Sharan, Paul Castrovillo
-
Patent number: 6849909Abstract: A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.Type: GrantFiled: September 28, 2000Date of Patent: February 1, 2005Assignee: Intel CorporationInventors: Rajendran Nair, Siva G. Narendra, Tanay Karnik, Vivek K. De
-
Publication number: 20040256645Abstract: A method for manufacturing a MOSFET equipped with a silicide layer over shallow source and drain junctions without leakage generation is provided. By restricting the temperature of manufacturing steps after the silicide formation below a critical temperature Tc, which is defined below as a function of a junction depth Dj from 20 nm to 60 nm, leakage generation is practically suppressed.Type: ApplicationFiled: April 12, 2004Publication date: December 23, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masakatsu Tsuchiaki, Shoko Tomita
-
Patent number: 6808962Abstract: The semiconductor device comprises an insulation layer formed on surfaces of semiconductor chips where the electrodes are formed, and a wiring layer formed on the insulation layer. The wiring layer formed on the insulation layer and the electrodes of the semiconductor chips are electrically connected to each other via connection members, such as wire bumps, etc. formed on the electrodes of the semiconductor chip.Type: GrantFiled: July 31, 2001Date of Patent: October 26, 2004Assignee: Dai Nippon Printing Co., Ltd.Inventor: Kunihiro Tsubosaki
-
Patent number: 6806573Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.Type: GrantFiled: April 5, 2001Date of Patent: October 19, 2004Assignee: Micron Technology, Inc.Inventor: Yongjun Hu
-
Publication number: 20040195689Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.Type: ApplicationFiled: April 27, 2004Publication date: October 7, 2004Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Wei-Jye Lin
-
Patent number: 6800911Abstract: A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.Type: GrantFiled: May 30, 2003Date of Patent: October 5, 2004Assignee: United Microelectronics CorporationInventor: Hirotomo Miura
-
Patent number: 6773978Abstract: Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.Type: GrantFiled: August 28, 2002Date of Patent: August 10, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Paul Raymond Besser, Eric Paton, James Pan
-
Publication number: 20040150111Abstract: In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.Type: ApplicationFiled: January 22, 2004Publication date: August 5, 2004Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Shuji Ikeda
-
Patent number: 6770972Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.Type: GrantFiled: November 12, 2002Date of Patent: August 3, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shih-der Tseng, Kuo-Ho Jao
-
Patent number: 6759683Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-SiC is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.Type: GrantFiled: August 27, 2001Date of Patent: July 6, 2004Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Melanie W. Cole, Pooran C. Joshi
-
Patent number: 6753606Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: GrantFiled: November 27, 2001Date of Patent: June 22, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Patent number: 6753563Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.Type: GrantFiled: November 1, 2001Date of Patent: June 22, 2004Assignee: Texas Instruments IncorporatedInventor: Robert H. Havemann
-
Patent number: 6750498Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.Type: GrantFiled: September 18, 2002Date of Patent: June 15, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Jiro Ida, Naoko Nakayama
-
Publication number: 20040104480Abstract: An ultra thin film with very low electrical resistance is produced by forming a substrate of a substrate material which forms a metastable bond and depositing a conducting film on the substrate in a vacuum environment in which a base pressure is reduced to a value below 10−5 Torr. The film is a metal, metallic alloy, or multilayered film which includes at least one metallic layer. A 0.1 nm thick manganese film deposited in this way on a germanium substrate has a resistivity which at room temperature is lower than the resistivity of metal films of aluminum and copper with the same thickness prepared the same way.Type: ApplicationFiled: September 10, 2003Publication date: June 3, 2004Inventor: Klaus Schroder
-
Patent number: 6744105Abstract: A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.Type: GrantFiled: March 5, 2003Date of Patent: June 1, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Cinti Xiaohua Chen, Hiroyuki Kinoshita, Jeff P. Erhardt, Weidong Qian, Jean Yee-Mei Yang
-
Patent number: 6737319Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.Type: GrantFiled: November 21, 2002Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Noboru Morimoto, Masazumi Matsuura, Kinya Goto
-
Patent number: 6724085Abstract: A semiconductor device miniaturizing the plane sizes of memory cells and a peripheral circuit part for a logic circuit and reducing wiring resistance and ensuring the degree of freedom in layout of wires on an interlayer isolation film. The semiconductor device comprises an active region included in a transistor formed on a semiconductor substrate, a wire formed on the semiconductor substrate, an interlayer isolation film covering the active region and the wire and a plug wire having a shape overlapping with both of the wire and the active region in plane, and the plug wire electrically connects the wire and the active region with each other.Type: GrantFiled: August 8, 2002Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventor: Kazuo Tomita
-
Patent number: 6713872Abstract: A first silicon oxide film is formed in such a manner as to cover source/drain regions of a transistor. A conductive pad is provided in the first silicon oxide film in such a manner that one end surface thereof is connected to each source/drain region and the other end surface thereof is exposed to the surface of the first silicon oxide film. A second silicon oxide film is formed on the first silicon oxide film and the pad. A conductive layer functioning as plug is provided in the second silicon oxide film in such a manner that one end surface thereof is in contact with the pad and the other end surface thereof is connected to an interconnection layer. The surface of the first silicon oxide film is smoothly continuous to the other end surface of the pad at the same level. The conductive layer as the plug is formed in such a manner as to be smaller in size than the pad and to be in contact with the central portion of the pad.Type: GrantFiled: April 3, 2002Date of Patent: March 30, 2004Assignee: Renesas Technology Corp.Inventor: Yoshinori Tanaka
-
Patent number: 6707117Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.Type: GrantFiled: October 31, 2002Date of Patent: March 16, 2004Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer, Andy Strachon, Peter Johnson
-
Patent number: 6693354Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.Type: GrantFiled: August 30, 2002Date of Patent: February 17, 2004Assignee: Micron Technology Inc.Inventors: Gary Chen, Li Li, Yongjun Jeff Hu
-
Patent number: 6683357Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal suicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.Type: GrantFiled: October 25, 2002Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
-
Patent number: 6683381Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.Type: GrantFiled: June 20, 2001Date of Patent: January 27, 2004Assignee: Matsushita Electric Industrsial Co., Ltd.Inventor: Takeshi Harada
-
Patent number: 6657301Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.Type: GrantFiled: December 20, 2001Date of Patent: December 2, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyoshi Maekawa, Yasuhiro Kanda
-
Patent number: 6642620Abstract: Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or more than completely offset any loss of dopant due to the hot hydrogen clean. A protective conductive layer such as a metal silicide is then formed over the contact area in situ. The resulting integrated circuit has contacts with interfaces such as a silicide interfaces to contact areas having a particularly favorable dopant profile and concentration adjacent the silicide interfaces.Type: GrantFiled: April 20, 2001Date of Patent: November 4, 2003Assignee: Micron Technology, Inc.Inventors: Sujit Sharan, Gurtej S. Sandhu
-
Patent number: 6635913Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.Type: GrantFiled: December 27, 2001Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
-
Patent number: 6614083Abstract: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display device having a low electric resistivity can be obtained.Type: GrantFiled: March 16, 2000Date of Patent: September 2, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama
-
Patent number: 6605490Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.Type: GrantFiled: July 12, 2002Date of Patent: August 12, 2003Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
-
Patent number: 6597050Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.Type: GrantFiled: May 19, 2000Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Peter Brian Gray, Kenneth Knetch Kieft, III, Nicholas Theodore Schmidt, Stephen St. onge
-
Publication number: 20030132521Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.Type: ApplicationFiled: November 12, 2002Publication date: July 17, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Shih-der Tseng, Kuo-Ho Jao
-
Patent number: 6586838Abstract: To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH4-based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH4-based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH4-based silicon oxide film. The SiH4-based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.Type: GrantFiled: July 23, 2001Date of Patent: July 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Noriaki Fujiki, Takeru Matsuoka, Hiroki Takewaka
-
Patent number: 6566753Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers.Type: GrantFiled: April 2, 2002Date of Patent: May 20, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Sheng Teng Hsu
-
Patent number: 6541830Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.Type: GrantFiled: August 8, 2000Date of Patent: April 1, 2003Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
-
Publication number: 20030057467Abstract: A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.Type: ApplicationFiled: October 21, 2002Publication date: March 27, 2003Inventor: Werner Juengling
-
Patent number: 6534837Abstract: The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.Type: GrantFiled: October 6, 2000Date of Patent: March 18, 2003Assignee: Intel CorporationInventors: Gang Bai, Brian S. Doyle
-
Patent number: 6534871Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.Type: GrantFiled: May 14, 2001Date of Patent: March 18, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-shen Maa, Douglas J. Tweet, Yoshi Ono, Fengyan Zhang, Sheng Teng Hsu
-
Patent number: 6534862Abstract: An electronic component includes an electronic component element electrically and mechanically joined to a base member, a plurality of electrode pads of the electronic component element and corresponding electrode lands of the base member being respectively joined together via bumps such that the electronic component element is arranged opposite to the base member. The bumps located along the peripheral portion of the electronic component element have a greater height than that of the bumps located at the central portion of the electronic component element.Type: GrantFiled: April 10, 2002Date of Patent: March 18, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Kazunobu Shimoe