Abstract: The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure.

Abstract: In a semiconductor device, a CoSi2 film is interposed between a pluglike contact and a barrier metal film as a silicide film. Consequently, excess reaction can be suppressed on a Ti/polysilicon interface between the pluglike contact or a pluglike local wire and the barrier metal film for stably lowering contact resistance.

Abstract: A method of forming a self-aligned silicide (salicide) with a double gate silicide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously thicker than silicide formations over the source and drain areas.

Abstract: A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.

Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: An integrated circuit includes a substrate having an etched surface and a non-etched surface. The etched surface contains circuit elements and the non-etched surface contains a bonding surface. The non-etched surface is located at a predetermined height from the etched surface. Bonding this integrated circuit with another substrate creates a wide-gap between the substrates that is preferably evacuated and hermetically sealed.

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.

Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiNx), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x<1) over the silicon substrate. The intermediate substrate structure is sintered to form a metal silicide. The silicidation of metal asymmetrically consumes less of the underlying silicon than the overlying silicon layer. The resulting structure is a mixed metal silicide/nitride layer which has a sufficient thickness to provide low sheet resistance without excessively consuming the underlying substrate.

Abstract: A semiconductor integrated circuit device and method of manufacturing the same is presented. The device comprises a first conductive line formed on a semiconductor substrate. An insulating layer formed on the first conductive line and the semiconductor substrate has a first contact hole exposing the first conductive line. A second conductive line consisting of a polysilicon layer and a silicide layer thereon is formed on the insulating layer including the first contact hole. The polysilicon layer of the second conductive line extends from the sidewall of the first contact hole to the top of the insulating layer so as to expose the first conductive line. The silicide layer of the second conductive line is directly connected to the exposed first conductive line in the first contact hole. Contact resistance between a bit line and a word line on the device can be reduced by directly contacting a silicide layer of the word line and a silicide layer of the bit line.

Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.

Abstract: Integrated circuit contact structures are fabricated by forming a first layer comprising niobium (Nb) on a silicon substrate and forming a second layer comprising a near noble metal on the first layer, opposite the silicon substrate. The near noble metal, also referred to as a Group VIII metal, is preferably cobalt (Co). The near noble metal has higher diffusion coefficient than the niobium and the silicon substrate. Annealing is then performed to diffuse at least some of the near noble metal through the first layer and react the diffused near noble metal with the silicon substrate to form a third layer comprising a near noble metal silicide, and to form a fourth layer comprising niobium-near noble metal alloy on the third layer. It has been found that the use of niobium can reduce substrate consumption compared to conventional cobalt titanium double-metal silicide fabrication processes.

Abstract: In a semiconductor device that uses a low-resistance ohmic contact and which is suitable for high-speed operation, the ohmic contacts are formed by a single-crystal CoSi2 film that is formed on the (100) surface of a silicon substrate.

Abstract: A semiconductor device having a substrate, an insulating film formed in the substrate, a conductive layer formed on the insulating film and having at least a part in contact with the insulating film made of a conductive material having a work function near a substantial center of an energy band gap of the substrate material and containing a predetermined amount of impurity, and a takeout electrode formed in the substrate and a method for producing the same.

Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta—Al—N material serves as a diffusion between (i) two conductor layers, (ii) a semiconductor layer and a conductor layer, (iii) an insulator layer and a conductor layer, (iv) an insulator layer and a semiconductor layer, or (v) two semiconductor layers. Another use is to promote adhesion of adjacent layers, such as between (i) two conductor layers, (ii) a conductor layer and an insulator layer, (iii) a semiconductor layer and a conductor layer, or (iv) two semiconductor layers. The Ta—Al—N material also is used to form a contact or electrode. The Ta—Al—N material includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen.

Abstract: The upper electrode of a capacitor is constituted of laminated films which respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A first silicon oxide film is formed in such a manner as to cover source/drain regions of a transistor. A conductive pad is provided in the first silicon oxide film in such a manner that one end surface thereof is connected to each source/drain region and the other end surface thereof is exposed to the surface of the first silicon oxide film. A second silicon oxide film is formed on the first silicon oxide film and the pad. A conductive layer functioning as a plug is provided in the second silicon oxide film in such a manner that one end surface thereof is in contact with the pad and the other end surface thereof is connected to an interconnection layer. The surface of the first silicon oxide film is smoothly continuous to the other end surface of the pad at the same level. The conductive layer as the plug is formed in such a manner as to be smaller in size than the pad and to be in contact with the central portion of the pad.

Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

Abstract: The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications.

Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.

Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: A conductive layer connecting structure has a barrier layer preventing mutual diffusion between silicon and platinum group elements even when they are heated to a high temperature. The conductive layer connecting structure includes a plug containing doped polycrystalline silicon, a barrier layer formed on the plug and containing titanium, silicon and nitrogen, and a lower electrode layer formed on the barrier layer and containing platinum.

Abstract: A method for manufacturing a bit line is disclosed. Such a method includes: forming a layer-insulation layer on the surface of a semiconductor substrate; forming a contact hole on a predetermined region of the layer-insulation layer; forming a first conductive layer on the upper surface of the layer-insulation layer and inside the contact hole, the first conductive layer being made of a metal; forming a second conductive layer on the upper surface of the first conductive layer, the second conductive layer being made of a metal; and patterning the first and the second conductive layers together. The bit line made of a metal is manufactured to be integrated with a plug. The first conductive layer is formed by sputtering while the second conductive layer is formed by chemical vapor deposition, thereby shortening the process and improving the characteristics of the bit line.

Abstract: A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then deposited over the contact area and annealed, forming titanium silicide. A second embodiment comprises depositing titanium over a defined contact area. Silicon is then implanted in the deposited titanium layer and annealed, forming titanium silicide. A third embodiment comprises combining the methods of the first and second embodiments. In further embodiment, nitrogen, cobalt, cesium, hydrogen, fluorine, and deuterium are also implanted at selected times.

Abstract: A semiconductor substrate adapted to giga-scale integration (GSI) comprises a support, at least the surface of which is made of semiconductor, an electroconductive material layer, an insulating layer and a semiconductor layer arranged sequentially in the above order. The electroconductive material layer has at least in part thereof an electroconductive reacted layer obtained by causing two metals, a metal and a semiconductor, a metal and a metal-semiconductor compound, a semiconductor and a metal-semiconductor compound, or two metal-semiconductor compounds to react each other. An electroconductive reaction terminating layer that is made of a material that does not react with the reacted layer is arranged between the reacted layer and the insulating layer or the support.

Abstract: There is provided a semiconductor memory device with extremely less deterioration of characteristics of dielectric thin film and with high stability. A TaSiN barrier metal layer 13 is formed on a Pt upper electrode 12. This TaSiN barrier metal layer 13 has electrical conductivity and hydrogen-gas blocking property and besides has an amorphous structure stable in high temperature region without crystallizing even during firing for crystallization of an oxide ferroelectric thin film (SBT thin film) 11. Then, hydrogen gas generated during later formation of a second interlayer insulating film 15 is reliably blocked from invading into the oxide ferroelectric thin film 11, by which characteristic deterioration of the oxide ferroelectric thin film 11 due to hydrogen gas is prevented.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: An interlayer insulating film having contact holes is formed on a major surface of a semiconductor substrate. A metal silicide film is formed on the interlayer insulating film. A polycrystal silicon film extending from the inside of contact holes onto the metal silicide film is formed. A local interconnection line is constituted of the polycrystal silicon film and the metal silicide film.

Abstract: An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIPOS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.

Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSix, by chemical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer.

Abstract: A high impedance load for an integrated circuit device provides an undoped, or lightly doped, layer of epitaxial silicon. The epitaxial silicon layer is formed over a conductive region in a substrate, such as a source/drain region. A highly conductive contact, such as a refractory metal silicide interconnect layer, is formed on top of the epitaxial silicon layer. Preferably, the epitaxial silicon layer is formed using solid phase epitaxy, from excess silicon in the silicide layer, by annealing the device after the silicide layer has been deposited.

Abstract: A structure of a polysilicon via that includes a semiconductor substrate, a conducting layer on the substrate, a dielectric layer on the conducting layer, a polysilicon plug formed in the dielectric layer, a polysilicon layer on the polysilicon plug, and a silicide layer formed on the polysilicon layer. The polysilicon layer is electrically connected to the conducting layer through the polysilicon plug. The structure of a polysilicon via according to the invention prevents the occurrence of leakage currents in the presence of misalignment in the follow-up photolithography process.