Abstract: An apparatus comprises a plurality of conductive elements arranged within at least a first conductive layer and a dielectric layer comprising a plurality of microcapsules. The first conductive layer is arranged on a first side of the dielectric layer. The apparatus further comprises monitoring circuitry coupled with the plurality of conductive elements and configured to detect a change in an electrical parameter for at least a first conductive element of the plurality of conductive elements. The change in the electrical parameter indicates a physical intrusion of the dielectric layer that causes a rupture of one or more microcapsules of the plurality of microcapsules.

Abstract: A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

Abstract: A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.

Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

Abstract: Disclosed is a method of forming a nitride film on a substrate to be processed (“processing target substrate”) having a carbon-containing film that contains a carbon atom. The method includes placing the processing target substrate within a processing container of a film forming apparatus, and forming a first nitride film on the carbon-containing film by plasma of a first reaction gas including a gas of nitride species having no hydrogen atom, and an inert gas.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked body that alternately includes a plurality of first films and a plurality of second films on a substrate. The method further includes performing a first process of forming N2 holes having N kinds of depths in the stacked body where N is an integer of three or more. The method further includes performing a second process of processing the N2 holes so as to have N2 kinds of depths after performing the first process.

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: A component-embedded resin substrate (1) includes a plurality of resin layers (2) made of a first resin and laminated on one another, and a component (3) arranged to be surrounded by each resin layer (2) in a first group (8) which is a group of two or more resin layers arranged successively in a thickness direction included in the plurality of resin layers (2). An auxiliary resin portion (9) made of a second resin different from the first resin is arranged to be in contact with and along at least one of surfaces of the component (3).

Abstract: The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.

Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.

Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: Provided are methods of sealing open pores of a surface of a porous dielectric material using an initiated chemical vapor deposition (iCVD) process. In one example method of sealing open pores, since the polymer thin film having a significantly thin thickness may be formed by a solvent-free vapor deposition method without plasma treatment, it is possible to minimize deterioration of characteristics of the dielectric material vulnerable to plasma and a chemical solution.

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a memory cell on a homogeneous bottom electrode via (BEVA) top surface. In some embodiments, the integrated circuit comprises a conductive wire, a via dielectric layer, a via, and a memory cell. The via dielectric layer overlies the conductive wire. The via extends through the via dielectric layer to the conductive wire, and has a first sidewall, a second sidewall, and a top surface. The first and second sidewalls of the via are respectively on opposite sides of the via, and directly contact sidewalls of the via dielectric layer. The top surface of the via is homogenous and substantially flat. Further, the top surface of the via extends laterally from the first sidewall of the via to the second sidewall of the via. The memory cell is directly on the top surface of the via.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; removing the second gate structure and part of the fin-shaped structure to forma first trench; forming a dielectric layer into the first trench; and planarizing part of the dielectric layer to form a single diffusion break (SDB) structure. Preferably, the top surfaces of the SDB structure and the first gate structure are coplanar.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by an inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode is disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.

Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Abstract: A field programmable gate array comprising: plurality of functional blocks at least one of the functional blocks comprising at least one function, at least one of the functions using a parameter, wherein the functional blocks are adapted to perform the at least one function in a calculation phase; a data conveyor comprising a plurality of data slots, wherein each functional block is, in a data transfer phase, adapted to receive input data from one or more predefined first slots and/or to provide output data into one or more predefined second slots; and a configuration circuit adapted to configure the parameter for the at least function using the parameter and to define the one or more first slots and/or the one or more second slots for at least one functional block, wherein the field programmable gate array is adapted to cyclically repeat the data transfer phase and calculation phase.

Abstract: There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

Abstract: Structures of and methods for fabricating fine-scale interconnects and fuses are disclosed. A “mushroom”-type structure with a narrow stalk supporting a wider cap can be used for fine-scale interconnects with widths on the scale of hundreds of nanometers that have low resistivity. Micro-air bridges can be introduced by omitting the stalk in sections of the interconnect, allowing the interconnect to bridge over obstacles. The mushroom-type micro-air bridge structure can also be modified to create fine-scale fuses that have low resistivity overall and sections of significantly higher resistivity where the micro-air bridges exist. The significantly higher resistivity results in preferential fusing at the micro-air bridges. Both mushroom interconnects and mushroom fuses can be fabricated using electron beam lithography.

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.

Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.

Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.

Abstract: Structures of and methods for fabricating fine-scale interconnects are disclosed. A “mushroom”-type structure with a narrow stalk supporting a wider cap can be used for fine-scale interconnects with widths on the scale of hundreds of nanometers that have low resistivity. Micro-air bridges can be introduced by omitting the stalk in sections of the interconnect, allowing the interconnect to bridge over obstacles.

Abstract: Semiconductor devices and methods of forming the same are described. An embodiment is a device including a pad on a substrate. A passivation film is on the substrate and covering at least a portion of the pad. A first conductive feature is on the pad and has a planar top surface, with the first conductive feature having a first height as measured from the pad to the planar top surface of the first conductive feature. A second conductive feature is on the passivation film and has a non-planar top surface, with the second conductive feature having a second height as measured from the passivation film to the non-planar top surface of the second conductive feature.

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Abstract: A sound transducer assembly for generating and/or detecting sound waves in the audible wavelength spectrum includes a membrane, a cavity and a MEMS printed circuit board unit. A MEMS printed circuit board unit for a sound transducer assembly for generating and/or detecting sound waves in the audible wavelength spectrum includes a multi-layer piezoelectric structure embedded in a printed circuit board. The printed circuit board includes a membrane, which the multi-layer piezoelectric structure can oscillate or detect oscillations thereof.

Abstract: A first metal layer is provided on a main surface side of a substrate. A second metal layer is formed on the first metal layer. A solder layer is provided on the second metal layer. An insulating member is structured so that an end of the first metal layer is partially connected to an end of the second metal layer.

Abstract: An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.

Abstract: Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor, including a drain electrode; a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.