Abstract: Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain Schottky electrode disposed in the recess of the barrier layer, the recessed-drain Schottky electrode contacting the drain electrode.

Abstract: Optical films, and organic light-emitting display apparatuses employing the same, include a high refractive index pattern layer including a first surface and a second surface facing each other, wherein the first surface includes a pattern having a plurality of grooves. The plurality of grooves each have a curved surface and a depth greater than a width thereof. The high refractive index pattern layer is formed of a material having a refractive index greater than 1. The optical films, and the organic light-emitting display apparatuses, further include a low refractive index pattern layer formed of a material having a refractive index smaller than the refractive index of the material constituting the high refractive index pattern layer. The low refractive index pattern layer includes a filling material for filling the plurality of grooves.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

Abstract: A method comprises epitaxially growing a gallium nitride (GaN) layer over a silicon substrate, epitaxially growing a donor-supply layer over the GaN layer, and etching a portion of the donor-supply layer. The method also comprises depositing a passivation layer over the donor-supply layer and filling the etched portion of the donor-supply layer, forming a source and a drain on the donor-supply layer, and forming a gate structure between the source and the etched portion of the donor-supply layer. The method further comprises depositing contacts over the gate structure, the source, and the drain.

Abstract: A transistor device includes a heterostructure body having a source, a drain spaced apart from the source and a two-dimensional charge carrier gas channel between the source and the drain. The transistor device further includes a piezoelectric gate on the heterostructure body. The piezoelectric gate is operable to control the channel below the piezoelectric gate by increasing or decreasing a force applied to the heterostructure body responsive to a voltage applied to the piezoelectric gate.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Abstract: A semiconductor device that can more efficiently absorb a stored hole includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, a second electrode, a control electrode, and a third electrode. The second semiconductor layer is provided on the first semiconductor layer and has a band gap narrower than that of the first semiconductor layer. The second semiconductor layer includes a first portion and a second portion which is provided together with the first portion and contains an activated acceptor. The third semiconductor layer is provided on the first portion and has a band gap wider than or equal to the band gap of the second semiconductor layer. The first and the second electrodes are provided on the third semiconductor layer. The control electrode is provided between the first electrode and the second electrode. The third electrode is provided on the second portion.

Abstract: Composite epitaxial materials that comprise semimetallic ErAs nanoparticles or nanoislands epitaxially embedded in a semiconducting In0.53Ga0.47As matrix both as superlattices and randomly distributed throughout the matrix are disclosed. The presence of these particles increases the free electron concentration in the material while providing scattering centers for phonons. Electron concentration, mobility, and Seebeck coefficient of these materials are discussed and their potential for use in thermoelectric power generators is postulated. These composite materials in accordance with the present invention have high electrical conductivity, low thermal conductivity, and a high Seebeck coefficient. The ErAs nanoislands provides additional scattering mechanism for the mid to long wavelength phonon—the combination reduces the thermal conductivity below the alloy limit.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Abstract: A semiconductor epitaxial structure is provided, which includes: a nitride nucleation layer, formed on a substrate including silicon, sapphire, patterned sapphire substrate (PSS) or silicon carbide, a nitride layer on the nitride nucleation layer and an multi-layer structure in the nitride layer. The multi-layer structure includes a first intermediate layer and a second intermediate layer formed on the first intermediate layer. The first intermediate layer includes AlGaN, the second intermediate layer includes AlGaN or aluminum nitride, and the average composition of Al in the first intermediate layer is less than that in the second intermediate layer. A method for forming a semiconductor epitaxial structure is provided. The semiconductor epitaxial structure according to the present disclosure can not decrease the crystalline quality when a compressive stress is introduced, which may avoid a crack phenomenon or quality degradation caused by the change of temperature.

Abstract: A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

Abstract: A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of AlxGa1?xN (0?x?1) is stacked, and includes a doping layer whose carbon concentration is 1×1018 to 1×1021 cm?3 and whose Si concentration is 1×1017 to 1×1020 cm?3, a thickness of the doping layer is 15% or more of the total thickness of the buffer layer.

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract: Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (AlX1Ga1-X1)As (0?X1?1) and a barrier layer which comprises a composition expressed by the composition formula of (AlX2Ga1-X2)As (0<X2?1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (AlX3Ga1-X3)Y1In1-Y1P (0?X3?1, 0<Y1?1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.

Abstract: Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes inorganic gases, organic vapors, biomolecules, viruses and the like. A number of embodiments of capacitive sensors having alternative architectures are described. Particular examples include integrated cell membranes and membrane-like structures in nanoelectronic sensors.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.

Abstract: Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling.

Abstract: Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.

Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semi-conductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.

Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.

Abstract: Techniques for manufacturing optical devices, such as light emitting diodes (LEDs) using a separation process of thick gallium and nitrogen containing substrate members, are described.

Abstract: A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate, a transition layer disposed on the initial buffer layer, and a device structure disposed on the transition layer. The transition layer includes at least one of AlxGa1-xN (where 0<x<1) layers provided on the initial buffer layer and an inserted buffer layer provided at least one of between the AlxGa1-xN layers, at a lower end portion of the transition layer, or at an upper end portion of the transition layer.

Abstract: A photodetector includes a substrate, a graphene layer disposed on the substrate, a first electrode disposed on the graphene layer, and a second electrode disposed on the graphene layer, where the first and second electrodes are spaced apart from each other, and where each of the first and second electrodes comprises a complex transparent electrode. The complex transparent electrode of the first electrode may have a different composition from the complex transparent electrode of the second electrode.

Abstract: A method for manufacturing graphene by vapor phase epitaxy on a substrate comprising a surface of SiC, characterized in that the process of sublimation of silicon from the substrate is controlled by a flow of an inert gas or a gas other than an inert gas through the epitaxial reactor. Graphene obtained by this method.

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract: A light emitting diode including a substrate, a p-type and n-type semiconductor layers, an active layer, a first and second electrodes is provided. The active layer is located between the n-type and p-type semiconductor layers, and includes i quantum wells and (i+1) quantum barrier layers, each quantum well is located between any two of the quantum barrier layers, each of k quantum wells among the i quantum wells is constituted of a light emitting layer and an auxiliary layer, in which an indium concentration of the auxiliary layer is greater than an indium concentration of the light emitting layer, where i and k are natural numbers greater than or equal to 1 and k?i. The first electrode and second electrodes are located on the n-type semiconductor layer and the p-type semiconductor layer, respectively.

Abstract: Exemplary embodiments of the present disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.

Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.

Abstract: The present invention discloses a method of heteroepitaxial growth enabling the successful growth of thin films of GaN and III-nitride semiconductor heterostructures of (0001) orientation with III metal-face polarity on diamond substrates being either polycrystalline or single crystal with various crystallographic orientations. The method uses a thin AlN nucleation layer on the diamond substrate with thickness equal or less than 5 nm, grown by Molecular Beam Epitaxy (MBE) using a nitrogen plasma source. The invention enables the development of very high power metal-face III-nitride devices, such as High Electron Mobility Transistors, on single crystal or polycrystalline diamond substrates. The method is also applicable for other element IV substrates with diamond crystal structure.

Abstract: A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.

Abstract: An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.

Abstract: Provided is a self-supporting gallium nitride substrate useful as an alternative material for a gallium nitride single crystal substrate, which is inexpensive and also suitable for having a large area. This substrate is composed of a plate composed of gallium nitride-based single crystal grains, wherein the plate has a single crystal structure in the approximately normal direction. This substrate can be manufactured by a method comprising providing an oriented polycrystalline sintered body; forming a seed crystal layer composed of gallium nitride on the sintered body so that the seed crystal layer has crystal orientation mostly in conformity with the crystal orientation of the sintered body; forming a layer with a thickness of 20 ?m or greater composed of gallium nitride-based crystals on the seed crystal layer so that the layer has crystal orientation mostly in conformity with crystal orientation of the seed crystal layer; and removing the sintered body.

Abstract: Disclosed is a light-emitting device (1) including a light-emitting element (2) emitting primary light, and a light converter (3) absorbing a part of the primary light emitted from the light-emitting element (2) and emitting secondary light having a longer wavelength than the primary light. The light converter (3) contains a green light-emitting phosphor (4) and a red light-emitting phosphor (5). The green light-emitting phosphor (4) is composed of at least one phosphor selected from a divalent europium-activated oxynitride phosphor substantially represented by the following formula: EuaSibAlcOdNe and a divalent europium-activated silicate phosphor substantially represented by the following formula: 2(Ba1-f-gMIfEug)O.SiO2, while the red light-emitting phosphor (5) is composed of at least one phosphor selected from tetravalent manganese-activated fluoro-tetravalent metalate phosphors substantially represented by the following formulae: MII2(MIII1-hMnh)F6 and/or MIV(MIII1-hMnh)F6.

Abstract: An ultraviolet light emitting diode package for emitting ultraviolet light is disclosed. The ultraviolet light emitting diode package comprises an LED chip emitting light with a peak wavelength of 350 nm or less, and a protective member provided so that surroundings of the LED chip is covered to protect the LED chip, the protective member having a non-yellowing property to energy from the LED chip.

Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.

Abstract: A film 3 of a nitride of a group 13 element is grown on a seed crystal substrate 11 by flux process from a melt containing a flux and a group 13 element under nitrogen containing atmosphere. The film 3 of a nitride of a group 13 element includes an inclusion distributed layer 3a in a region distant from an interface of the film of a nitride of group 13 element on the side of the seed crystal substrate 11 and containing inclusions derived from components of the melt, and an inclusion depleted layer 3b, with the inclusion depleted. provided on the layer 3a.

Abstract: An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the anode of the second GaN diode is electrically connected to the leadframe.

Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.

Abstract: A transistor that offers a high dielectric breakdown voltage of a gate insulating film with limited reduction of the current flowing between drain and source electrodes. The transistor has a semiconductor layer, a gate insulating film on the semiconductor layer, a gate electrode on the gate insulating film, and a source electrode and a drain electrode disposed on the semiconductor layer with the gate electrode therebetween. The concentration of the impurities contained in the gate insulating film is on a downward gradient starting at the surface of the gate insulating film on the semiconductor layer side and ending at the surface of the gate insulating film on the gate electrode side.