Abstract: An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.

Abstract: A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions.

Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.

Abstract: A semiconductor light-emitting device includes a light-emitting structure that includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, an electrode layer contacting one of the first conductive semiconductor layer and the second conductive semiconductor layer, and a bonding conductive layer connected to the electrode layer. The bonding conductive layer includes a main bonding layer having a recess area defined by a stepped portion on a surface opposite to a surface facing the electrode layer, and a filling bonding layer filling at least a part of the recess area.

Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.

Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.

Abstract: An ultraviolet (UV) photo-detecting device, including: a first nitride layer; a secondary light absorption layer disposed on the first nitride layer; a primary light absorption layer disposed on the secondary light absorption layer; and a Schottky junction layer disposed on the primary light absorption layer. The secondary light absorption layer includes a nitride layer having lower band-gap energy than the primary light absorption layer.

Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (?-Al2O3, ?-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or ?-Fe2O3) is used.

Abstract: There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer situated over a group III-V channel layer, and a source electrode and a drain electrode. The group III-V merged cascode transistor also includes an enable gate disposed in a recess extending substantially through the group III-V barrier layer, and an operational gate disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate.

Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a source electrode provided above the nitride semiconductor layer, a drain electrode provided above the nitride semiconductor layer at a side opposite to the source electrode with respect to the gate electrode, a first silicon nitride film provided above the nitride semiconductor layer between the drain electrode and the gate electrode, and a second silicon nitride film provided between the nitride semiconductor layer and the gate electrode, an atomic ratio of silicon to nitrogen in the second silicon nitride film being lower than an atomic ratio of silicon to nitrogen in the first silicon nitride film.

Abstract: This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefiting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Abstract: A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.

Abstract: A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region, and a plurality of first bridges electrically connecting the plurality of second electrodes. The matrix electrode structure comprises a plurality of first electrodes arranged on the epitaxial stack and a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes. One of the bridges is arranged between two of the second electrodes and crossed over one of the first electrodes.

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

Abstract: A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Abstract: According to an embodiment, there is provided a method of fabricating an epitaxial wafer, which includes preparing a wafer in a susceptor; and growing an epitaxial layer on the wafer, wherein the growing of the epitaxial layer on the wafer includes supplying a raw material into the susceptor; growing the epitaxial layer on the wafer at a first growth rate; and growing the epitaxial layer on the wafer at a second growth rate higher than the first growth rate. According to an embodiment, there is provided a silicon carbide epitaxial wafer which includes a silicon carbide wafer; and a silicon carbide epitaxial layer on the silicon carbide wafer wherein a surface defect formed on the silicon carbide epitaxial layer is 1 ea/cm2 or less.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: This invention provides a method for manufacturing composite wafers in which at least two composite wafers can be obtained from one donor wafer, and in which the chamfering step can be omitted. Provided is a method for manufacturing composite wafers comprising: bonding surfaces of at least two handle wafers and a surface of a donor wafer which has a diameter greater than or equal to a sum of diameters of the at least two handle wafers and which has a hydrogen ion implantation layer formed inside thereof by implanting hydrogen ions from the surface of the donor wafer, to obtain a bonded wafer; heating the bonded wafer at 200° C. to 400° C.; and detaching a film from the donor wafer along the hydrogen ion implantation layer of the heated bonded wafer, to obtain the composite wafers having the film transferred onto the at least two handle wafers.

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit.

Abstract: A material including: graphene; and an inorganic material having a crystal system, wherein a crystal plane of the inorganic material is oriented parallel to the (0001) plane of the graphene. The crystal plane of the inorganic material has an atomic arrangement of a hexagon, a tetragon, or a pentagon.

Abstract: To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state.

Abstract: A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.

Abstract: The integration of bilayer graphene with an absorption enhancing sub-wavelength antenna provides an infrared photodetector capable of real-time spectral tuning without filters at nanosecond timescales.

Abstract: A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction.

Abstract: A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation.

Abstract: The present application discloses a composite substrate with a protective layer for preventing metal from diffusing, comprising: a thermally and electrically conductive layer (2) having a melting point of greater than 1000° C., and a GaN mono-crystalline layer (1) located on the thermally and electrically conductive layer (2). At least the side wall of the composite substrate is cladded with a protective layer (3) for preventing metal from diffusing. The composite substrate not only takes account of the homoepitaxy required for GaN epitaxy and improves the quality of the crystals, but also can be used directly to prepare LEDs with vertical structures and significantly reduce costs. The disclosed composite substrate effectively avoids the pollution of experimental instruments by the diffusion and volatilization of a metal material during the growth of MOCVD at high temperature.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Abstract: Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: According to one embodiment, a photoelectric converting layer, a charge accumulating layer, and a light collecting unit are provided. The photoelectric converting layer is formed at a back surface side of a semiconductor substrate. The charge accumulating layer is formed at a front surface side of the semiconductor substrate, and accumulates charges photoelectric-converted by the photoelectric converting layer. The light collecting unit makes light incident to the back surface side of the semiconductor substrate to be collected on the photoelectric converting layer not to be incident to the charge accumulating layer.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: Optical films, and organic light-emitting display apparatuses employing the same, include a high refractive index pattern layer including a first surface and a second surface facing each other, wherein the first surface includes a pattern having a plurality of grooves. The plurality of grooves each have a curved surface and a depth greater than a width thereof. The high refractive index pattern layer is formed of a material having a refractive index greater than 1. The optical films, and the organic light-emitting display apparatuses, further include a low refractive index pattern layer formed of a material having a refractive index smaller than the refractive index of the material constituting the high refractive index pattern layer. The low refractive index pattern layer includes a filling material for filling the plurality of grooves.

Abstract: According to one embodiment, a semiconductor device includes a nitride semiconductor layer, a first electrode provided on the layer, a second electrode provided on the layer, a insulating film provided on the layer, a first control electrode provided on the film, and a conductor provided on the film. The first control electrode includes a first edge, and a second edge. The first edge is provided between the second edge and the first electrode. The conductor includes a first portion and a third edge positioned between the first portion and the first electrode. An electric field strength at a first region is substantially equal to an electric field strength at a second region. The first region overlaps the first edge when projected onto a plane perpendicular to a stacking direction. The second region overlaps the third edge when projected onto the plane.

Abstract: Provided are high electron mobility transistors (HEMTs), methods of manufacturing the HEMTs, and electronic devices including the HEMTs. An HEMT may include an impurity containing layer, a partial region of which is selectively activated. The activated region of the impurity containing layer may be used as a depletion forming element. Non-activated regions may be disposed at opposite side of the activated region in the impurity containing layer. A hydrogen content of the activated region may be lower than the hydrogen content of the non-activated region. In another example embodiment, an HEMT may include a depletion forming element that includes a plurality of regions, and properties (e.g., doping concentrations) of the plurality of regions may be changed in a horizontal direction.

Abstract: A Schottky diode is disclosed. The Schottky diode includes: a substrate, a first-type buried layer in the substrate, a cathode region, an anode region surrounding the cathode region, and a first-type guard ring surrounding the anode region and connected to the first-type buried layer. The cathode region preferably includes a high-voltage second-type lightly doped drain in the substrate, a first-type well surrounding the high-voltage second-type lightly doped drain, and a first-type doping region in the first-type well and surrounding the high-voltage second-type lightly doped drain.

Abstract: A semiconductor light-emitting device made of a nitride-based semiconductor includes a semiconductor stacked structure having a nonpolar plane or a semipolar plane as a principal plane, and including an active layer for emitting polarized light. The semiconductor light-emitting device includes a striped structure which is provided in a position intersecting an exit path of the polarized light and includes a plurality of recesses. An angle formed between the extension direction of the recesses and the polarization direction of the polarized light is from 0° to 45°. The recesses have a minute uneven structure (texture) at at least part of a surface of each recess, the minute uneven structure being shallower than the depth of each recess.

Abstract: According to one embodiment, a crystal includes thallium bromide (TlBr), one or more positively charged dopants, and one or more negatively charged dopants. According to another embodiment, a system includes a monolithic crystal including thallium bromide (TlBr), one or more positively charged dopants, and one or more negatively charged dopants; and a detector configured to detect a signal response of the crystal.

Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Abstract: A photo-detecting device includes a first nitride layer, a low-current blocking layer disposed on the first nitride layer, a light absorption layer disposed on the low-current blocking layer, and a Schottky junction layer disposed on the light-absorption layer. The low-current blocking layer includes a multilayer structure.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.