Abstract: A method is described for forming at least one metal contact on a surface of a semiconductor and a device with at least one metal contact. The method is used for forming at least one metal contact (60) on a surface (11) of a semiconductor (10) and has the steps of: applying a metal layer (20) of palladium onto the semiconductor surface (11), applying a mask (40, 50) onto the metal layer (20), and structuring the palladium of the metal layer (20) using the mask (40, 50), wherein lateral deposits (21) of the metal are formed on sidewalls of the mask by the structuring so that the mask is embedded between the deposits (21) and the structured metal layer (20?) after the structuring. Since the mask is conductive, it can remain embedded in the metal. The deposits and the mask form a part of the contact.

Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.

Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used.

Abstract: A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×1015 cm?3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.

Abstract: A microbolometer device integrated with CMOS and BiCMOS technologies and methods of manufacture are disclosed. The method includes forming a microbolometer unit cell, comprises damaging a portion of a substrate to form a damaged region. The method further includes forming infrared (IR) absorbing material on the damaged region. The method further includes isolating the IR absorbing material by forming a cavity underneath the IR absorbing material.

Abstract: According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

Abstract: A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron gas in the first layer, a source electrode provided on the second layer, a drain electrode provided on the second layer, a gate electrode provided between the source electrode and the drain electrode on the second layer, and a first insulating layer provided between the gate electrode and the drain electrode on the second layer, the first insulating layer being a first oxide of at least one first element selected from the group consisting of Hf, Zr, Ti, Al, La, Y, and Sc, the first insulating layer containing 5×1019 cm?3 or more of at least one second element selected from the group consisting of F, H, D, V, Nb, and Ta.

Abstract: In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured.

Abstract: An optoelectronic semiconductor chip includes a semiconductor body that has a semiconductor layer sequence and at least one opening that extends through a second semiconductor layer into a first semiconductor layer. The chip also includes a support, which includes at least one recess, and a metallic connecting layer between the semiconductor body and the support. The metallic connecting layer includes a first region and a second region. The first region is connected to the first semiconductor layer in an electrically conductive manner through the opening and the second region is connected to the second semiconductor layer in an electrically conductive manner. A first contact is connected to the first region in an electrically conductive manner through the recess or a second contact is connected to the second region in an electrically conductive manner through the recess.

Abstract: The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (AlxGa1-xN) sub-layers. Each of the sub-layers has a respective value for x that is between 0 and 1. A value of x for each sub-layer is a function of its position within the second buffer layer. A first gallium nitride (GaN) layer is epitaxially grown over the second buffer layer. A third buffer layer is then epitaxially grown over the first GaN layer. A second GaN layer is then epitaxially grown over the third buffer layer.

Abstract: A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer.

Abstract: An optoelectronic component includes a semiconductor layer structure having a quantum film structure, and a p-doped layer arranged above the quantum film structure, wherein the p-doped layer includes at least one first partial layer and a second partial layer, and the second partial layer has a higher degree of doping than the first partial layer.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

Abstract: A high electron mobility transistor is provided, which includes a substrate, a superlattice structure formed on the substrate, and a transistor epitaxial structure formed on the superlattice structure such that the superlattice structure is interposed between the substrate and the transistor epitaxial layer. As the high electron mobility transistor has the carbon-doped AlN/GaN superlattice structure between the substrate and the transistor epitaxial layer. Thus, the present invention can effectively reduce vertical leakage current, so as to improve the epitaxial quality and the breakdown voltage of the high electron mobility transistor.

Abstract: Techniques for processing materials for manufacture of gallium-containing nitride substrates are disclosed. More specifically, techniques for fabricating and reusing large area substrates using a combination of processing techniques are disclosed. The methods can be applied to fabricating substrates of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others. Such substrates can be used for a variety of applications including optoelectronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photo detectors, integrated circuits, transistors, and others.

Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Abstract: The present techniques provide a method for producing a Group III nitride semiconductor light-emitting device, with suppression of an increase in polarity inversion defect density. The production method includes an n-type semiconductor layer formation step, a light-emitting layer formation step, and a p-type semiconductor layer formation step. The p-type semiconductor layer formation step includes a p-type cladding layer formation step. The p-type cladding layer formation step includes a first p-type semiconductor layer formation step for forming a p-type AlGaN layer, a first semiconductor layer growth intermission step after the first p-type semiconductor layer formation step, and a p-type InGaN layer formation step after the first semiconductor layer growth intermission step. In the first semiconductor layer growth intermission step, a mixture of nitrogen gas and hydrogen gas is supplied to the substrate.

Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer.

Abstract: A semiconductor device includes: a substrate; a nitride semiconductor film on the substrate; a schottky electrode on the nitride semiconductor film; a first insulating film on the nitride semiconductor film, contacting at least part of a side surface of the schottky electrode, forming an interface with the nitride semiconductor film and formed of SiN; and a second insulating film covering the schottky electrode and the first insulating film and formed of AlO whose atomic layers are alternately disposed.

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

Abstract: Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials.

Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Abstract: A FinFET and methods for forming a FinFET are disclosed. In a method, first trenches are formed in a substrate. First isolation regions are then formed in the first trenches. An epitaxial region is epitaxially grown between the first isolation regions. A second trench is formed by etching in the epitaxial region, forming a plurality of fins. A second isolation region is formed in the second trench. A structure includes a substrate, a first fin on the substrate, a gate dielectric over the first fin, and a gate electrode over the gate dielectric. The first fin comprises an epitaxial layer having a stacking fault defect density less than 1*104 cm?3.

Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

Abstract: In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over the drift region and having source diffusions formed therein, a gate trench extending through the body region, and channel regions adjacent the gate trench. The channel regions are spaced apart along the gate trench by respective deep body implants. Each of the deep body implants is situated approximately under at least one of the source diffusions, and has a depth greater than a depth of the gate trench.

Abstract: A light emitting module including a driving unit and a light emitting diode is provided. The light emitting diode is electrically connected to the driving unit and the driving unit provides an operating current to make the light emitting diode emit light. The light emitting diode includes an n-type semiconductor layer, a light-emitting layer, an electron-blocking layer, and a p-type semiconductor layer. The electron-blocking layer has a thickness, and the thickness is smaller than or equal to 30 nm or is larger than or equal to 80 nm. The light-emitting layer is located between the electron-blocking layer and the n-type semiconductor layer. The electron-blocking layer is located between the p-type semiconductor layer and the light-emitting layer. A ratio of current density of the light emitting diode to the thickness is larger than 0 and is smaller than or equal to 2.

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Abstract: An n-type GaN layer made of n-type gallium nitride (GaN) is formed on a sapphire substrate. A plurality of island-phased layered structures are formed in random sizes between the n-type GaN layer and a p-type GaN layer that is made of p-type GaN. Each of the layered structures is configured by stacking multiple AlN layers made of aluminum nitride (AlN) and multiple InGaN layers made of indium gallium nitride (InGaN) on an AlN base layer. The respective layered structures emit lights of different wavelengths. This accordingly allows for emission of light in a wider wavelength range.

Abstract: A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.

Abstract: There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.

Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

Abstract: An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

Abstract: A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

Abstract: There is provided a method for producing a Group III nitride semiconductor light-emitting device having a low driving voltage, which is realized by steeply increasing the concentration of Mg within a p-type semiconductor layer. This production method includes the steps of forming an n-type contact layer, forming an n-side high electrostatic breakdown voltage layer, forming an n-side superlattice layer, forming a light-emitting layer, forming a p-type cladding layer, forming a p-type intermediate layer, and forming a p-type contact layer. The step of forming the p-type cladding layer includes supplying a dopant gas without supplying a first raw material gas (TMG) containing a Group III element during a first period TA1 and supplying the first raw material gas (TMG) and the dopant gas during a second period TA2 after the first period TA1 so as to grow a semiconductor layer.

Abstract: A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base. A depletion mode gallium nitride field-effect transistor (GaN FET) and an enhancement mode laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS FET) are also coupled with the base. The gate connector and a gate contact of the LDMOS FET are both included in a first electrical node, the source connector and a source contact of the LDMOS FET are both included in a second electrical node, and the drain connector and a drain contact of the GaN FET are both included in a third electrical node. The GaN FET and LDMOS FET together form a cascode that operates as an enhancement mode amplifier. The semiconductor package does not include an interposer between the GaN FET and the base or between the LDMOS FET and the base.

Abstract: A manufacturing method of a LED display is provided. A temporary substrate is provided, wherein the temporary substrate has a first adhesive layer and a plurality of first, second and third LED chips mounted on the first adhesive layer. A first transparent substrate is provided, the transparent substrate has a plurality of pixels disposed thereon, and each of the pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel respectively surrounded by a light-insulating structure. Then, the temporary substrate and the first transparent substrate are bonded together, such that each of the first, second and third LED chips is correspondingly mounted in each of the first sub-pixels, the second sub-pixels and the third sub-pixels. After that, the temporary substrate is removed. A LED display manufactured by said method is also provided.

Abstract: A method for depositing a Group III nitride semiconductor film on a substrate is provided that comprises: providing a sapphire substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; holding the substrate away from a substrate facing surface of a heater by a predetermined distance; heating the substrate to a temperature by using the heater whilst the substrate is held away from the substrate facing surface of the heater, and depositing a Group III nitride semiconductor film onto the conditioned surface of the substrate by a physical vapour deposition method whilst the substrate is held away from the substrate facing surface of the heater and forming an epitaxial Group III nitride semiconductor film with N-face polarity on the conditioned surface of the substrate.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device.

Abstract: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.

Abstract: In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.

Abstract: A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction.

Abstract: A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.

Abstract: A semiconductor device comprises a substrate, a patterned conductive layer, a first transistor structure and a second transistor structure. The patterned conductive layer is formed on the substrate. The first transistor structure includes a first source, a first gate and a first drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The second transistor structure includes a second source, a second gate and a second drain and is electrically connected to the patterned conductive layer by flip-chip bonding. The first gate is electrically connected to the second source through the patterned conductive layer, and the first source is electrically connected to the second drain through the patterned conductive layer.

Abstract: An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.