Alignment Marks Patents (Class 257/797)
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Patent number: 7807575Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. A partially fabricated integrated circuit device is also disclosed.Type: GrantFiled: November 29, 2006Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventor: Baosuo Zhou
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Patent number: 7807498Abstract: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.Type: GrantFiled: July 10, 2008Date of Patent: October 5, 2010Assignee: Seiko Epson CorporationInventors: Masanobu Shoji, Toru Fujita
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Publication number: 20100244287Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alex Hsu, Shih-Chi Fu, Feng-Jia Shiu, Chia-Shiung Tsai
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Publication number: 20100244288Abstract: A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.Type: ApplicationFiled: June 11, 2010Publication date: September 30, 2010Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: David C. Douglas, Ronald Ho, Robert J. Drost
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Publication number: 20100240192Abstract: An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.Type: ApplicationFiled: March 18, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroomi NAKAJIMA
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Publication number: 20100237514Abstract: The invention relates to a method for marking wafers, in particular wafers for solar cell production: The method comprises the steps of manufacturing a position line (21a, 21b, 21c) on a peripheral surface of a silicon ingot or column, the ingot or column extending in an axial direction and having a longitudinal axis in the axial direction, wherein the position line extends in the axial direction along substantially the whole ingot or column and is inclined with respect to the longitudinal axis. By this position line it is possible to determine the position of a wafer cut from the ingot or column within the ingot or column, respectively. Further, an individual identification pattern (20a, 20b, 20c) of lines on the peripheral surface of the silicon ingot or column is manufactured, the individual identification pattern of lines extending in axial direction over substantially the whole ingot or column and providing an individual coding which allows to identify the silicon ingot or column.Type: ApplicationFiled: June 13, 2007Publication date: September 23, 2010Applicant: Conergy AGInventors: Andre Richter, Marcel Krenzin, Jens Moecke
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Patent number: 7799673Abstract: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed.Type: GrantFiled: May 16, 2008Date of Patent: September 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Arai, Akihiro Kojima
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Publication number: 20100225011Abstract: A system and method for integrated circuit fabrication is provided. A wafer holding system includes a wafer carrier that holds the wafer at a specified alignment, and a top ring disposed on a top surface of the wafer and of the wafer carrier. The top ring holds the wafer and the wafer carrier together as a single unit. The wafer carrier includes an alignment mechanism to hold the wafer in the specified alignment.Type: ApplicationFiled: January 7, 2010Publication date: September 9, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-I Lee, Tsung-Ding Wang
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Patent number: 7791212Abstract: There is provided a hybrid mounted device that includes a element such as semiconductor laser diode (LD), and a board such as a silicon platform having formed thereon an optical waveguide. The LD is mounted to the silicon platform, and is optically coupled to the optical waveguide. The mounting position of the LD is determined by positioning first alignment marks formed on the board and second alignment marks formed on the LD. In this configuration, initial positional deviation amount measuring marks that can measure the initial positional deviation amount of the first alignment marks themselves are formed on the board. The mounting position of the is corrected to a position where the second alignment marks are shifted with respect to the first alignment marks according to the initial positional deviation amount measured from the initial positional deviation amount measuring marks.Type: GrantFiled: December 19, 2006Date of Patent: September 7, 2010Assignee: NEC CorporationInventors: Morio Takahashi, Hiroyuki Yamazaki, Yukari Deki
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Patent number: 7786607Abstract: A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.Type: GrantFiled: February 19, 2004Date of Patent: August 31, 2010Assignee: ASML Holding N.V.Inventor: Peter Kochersperger
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Patent number: 7785980Abstract: An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.Type: GrantFiled: May 15, 2007Date of Patent: August 31, 2010Assignee: Elpida Memory, Inc.Inventor: Kazushi Suzuki
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Patent number: 7785981Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.Type: GrantFiled: June 30, 2008Date of Patent: August 31, 2010Assignee: Sony CorporationInventors: Yuichi Yamamoto, Hayato Iwamoto
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Publication number: 20100214566Abstract: Alignment of layers during manufacture of a multi-layer sample is controlled by applying optical measurements to a measurement site in the sample. The measurement site includes two diffractive structures located one above the other in two different layers, respectively. The optical measurements include at least two measurements with different polarization states of incident light, each measurement including illuminating the measurement site so as to illuminate one of the diffractive structures through the other. The diffraction properties of the measurement site are indicative of a lateral shift between the diffractive structures. The diffraction properties detected are analyzed for the different polarization states of the incident light to determine an existing lateral shift between the layers.Type: ApplicationFiled: May 7, 2010Publication date: August 26, 2010Applicant: Nova Measuring Instruments, Ltd.Inventors: Boaz Brill, Moshe Finarov, David Scheiner
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Patent number: 7781901Abstract: A disclosed semiconductor device includes a semiconductor substrate including semiconductor integrated circuit forming areas; semiconductor integrated circuits formed on the semiconductor integrated circuit forming areas; and an alignment pattern formed on a periphery of at least one of the semiconductor integrated circuit forming areas.Type: GrantFiled: August 15, 2007Date of Patent: August 24, 2010Assignee: Mitsumi Electric Co., Ltd.Inventor: Yukihiro Tanemura
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Publication number: 20100207283Abstract: A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages.Type: ApplicationFiled: February 17, 2009Publication date: August 19, 2010Inventors: Ruisheng Wu, Yan Liu, Tao Feng
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Publication number: 20100207284Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Karen L. Holloway, Holly LaFerrara, Alexander L. Martin, Martin E. Powell, Timothy J. Wiltshire, Roger J. Yerdon
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Patent number: 7772710Abstract: A zero-order overlay target comprises a first zero-order line array fabricated on a first layer of a semiconductor structure, the first zero-order line array having a first pitch, and a second zero-order line array fabricated on a second layer of the semiconductor structure, the second zero-order line array having a second pitch. The second pitch may be different from the first pitch, and a portion of the second zero-order line array may be positioned to become optically coupled to a portion of the first zero-order line array when subject to an overlay measurement. Further, the second pitch may be variable. For example, the variable pitch may comprise a first set of features having a pitch approximately equal to the first pitch, a second set of features having a pitch different from the first pitch, and a third set of features having a pitch approximately equal to the first pitch.Type: GrantFiled: October 31, 2007Date of Patent: August 10, 2010Assignees: Sematech, Inc., National Institute of Standards and TechnologyInventors: Richard Silver, Pete Lipscomb, Bryan Barnes, Ravikirran Attota
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Publication number: 20100193974Abstract: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning.Type: ApplicationFiled: April 14, 2010Publication date: August 5, 2010Applicant: AU Optronics CorporationInventor: San-Chi Wang
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Publication number: 20100187686Abstract: A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.Type: ApplicationFiled: March 31, 2010Publication date: July 29, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Na-rae SHIN, Dong-han KIM
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Patent number: 7759808Abstract: The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.Type: GrantFiled: October 15, 2008Date of Patent: July 20, 2010Assignee: Elpida Memory, Inc.Inventor: Osamu Kindo
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Patent number: 7759707Abstract: A semiconductor substrate includes: a first semiconductor layer; an oxide layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the oxide layer; a first recess that is formed in the second semiconductor layer with extending from an upper face of the second semiconductor layer toward the first semiconductor layer, the first recess being formed at a position where an alignment mark for determining a forming position of an element which is to be built in the semiconductor substrate is to be formed; and an etching prevention layer that is inwardly formed from a position of an upper face of the first semiconductor layer, the position corresponding to the recess, the layer comprising a material that is prevented from being etched during etching of the first semiconductor layer.Type: GrantFiled: April 17, 2008Date of Patent: July 20, 2010Assignee: Fujifilm CorporationInventor: Shinji Uya
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Patent number: 7755090Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.Type: GrantFiled: October 9, 2007Date of Patent: July 13, 2010Assignee: Sony CorporationInventors: Takashi Abe, Nobuo Nakamura, Keiji Mabuchi, Tomoyuki Umeda, Hiroaki Fujita, Eiichi Funatsu, Hiroki Sato
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Patent number: 7755207Abstract: A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.Type: GrantFiled: February 28, 2006Date of Patent: July 13, 2010Assignee: Ricoh Company, Ltd.Inventors: Koichi Sogawa, Kiyoshi Yano, Tohru Haruki, Hidetsugu Miyake, Shouji Tochishita, Minoru Ohtomo, Kenji Nishihara
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Patent number: 7751047Abstract: A lithographic substrate provided with an alignment mark, the alignment mark having a plurality of features spaced apart from one another, each feature being spaced apart from adjacent features by a different distance is disclosed. Further, there is disclosed a method of aligning a lithographic substrate provided with an alignment mark which has a plurality of features spaced apart from one another, each feature being spaced apart from adjacent features by a different distance, the method including measuring a distance between two of the features on the substrate, comparing the distance with a recorded set of distances, and determining from the comparison the position of the substrate.Type: GrantFiled: August 2, 2005Date of Patent: July 6, 2010Assignee: ASML Netherlands B.V.Inventors: Fransiscus Godefridus Casper Bijnen, Henricus Wilhelmus Maria Van Buel
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Patent number: 7749690Abstract: Systems and methods are disclosed herein to provide die identification. For example, in accordance with an embodiment of the present invention, a wafer patterning technique is disclosed that provides multiple-exposure patterning to provide a unique identifying mark for each die on a wafer.Type: GrantFiled: June 30, 2004Date of Patent: July 6, 2010Assignee: Flir Systems, Inc.Inventors: James T. Woolaway, Glenn T. Kincaid, Eric A. Kurth, Robert F. Zausch, Glenn E. Williams
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Patent number: 7745945Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.Type: GrantFiled: October 10, 2006Date of Patent: June 29, 2010Assignee: STMicroelectronics Asia Pacific Pte. Ltd.Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
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Publication number: 20100155968Abstract: In one embodiment, a metrology target for determining a relative shift between two or more successive layers of a substrate may comprise; an first structure on a first layer of a substrate and an second structure on a successive layer to the first layer of the substrate arranged to determine relative shifts in alignment in both the x and y directions of the substrate by analyzing the first structure and second structure overlay.Type: ApplicationFiled: March 4, 2010Publication date: June 24, 2010Applicant: KLA-TENCOR CORPORATIONInventors: Mark Ghinovker, Vladimir Levinski
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Publication number: 20100155967Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).Type: ApplicationFiled: July 10, 2008Publication date: June 24, 2010Applicant: NXP B.V.Inventor: Heimo Scheucher
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Patent number: 7741652Abstract: An alignment device and applications thereof are disclosed. The device comprises a dam structure disposed on a first substrate, and a post disposed on a second substrate at a position corresponding to the dam structure. The dam structure comprises a groove. The post is disposed in the groove of the dam structure when bonding the first and second substrates.Type: GrantFiled: March 7, 2008Date of Patent: June 22, 2010Assignee: VisEra Technologies Company LimitedInventor: Hsiao-Wen Lee
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Patent number: 7741701Abstract: A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface with a laser beam, wherein the treated area is ablated or melted by the beam and re-solidifies into a more planar profile, thereby reducing areas of stress concentration and stress risers that contribute to cracking and chipping during wafer singulation. Preferably, the treated area has a width less than that of a scribe street, but wider than the kerf created by a wafer dicing blade. Consequently, when the wafer is singulated, the dicing blade will preferably saw through treated areas only. It will be understood that the method of the preferred embodiments may be used to treat other areas of stress concentration and surface discontinuities on the wafer, as desired.Type: GrantFiled: March 13, 2006Date of Patent: June 22, 2010Assignee: Texas Instruments IncorporatedInventors: Richard L. Mahle, Peter J. Sakakini
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Patent number: 7737567Abstract: A semiconductor substrate is provided. The substrate includes a first surface and an opposing second surface, wherein the first surface includes a marking in a centroid region of the first surface. The marking indicates a location of a center point on the first surface of the semiconductor substrate or identification data unique to the substrate. A system, methods of transporting and marking, and a device for reading the substrate markings are also provided.Type: GrantFiled: June 20, 2008Date of Patent: June 15, 2010Assignee: Crossing Automation, Inc.Inventors: Anthony C. Bonora, Raymond S. Martin, Michael Krolak
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Patent number: 7737566Abstract: Alignment marks for use on substrates. An exemplary implementation provides phase depth control. A grating mark, for example, can be etched on a silicon wafer with sub-wavelength segmentation in the spacing portion of the alignment grating's period. The sub-wavelength segmentation can be applied to the spaces or to the lines, or both, of an alignment grating to control the phase depth of the grating. By applying segmentation with a period smaller than the alignment light wavelength in either the space(s) and/or in the line(s) of the grating, the effective refractive index in that region can be manipulated. This change in the effective index will result in a change in the phase depth (optical path length). By varying the duty cycle of the sub-wavelength segmented region, the effective refractive index can be controlled, thereby providing selective control over the phase depth.Type: GrantFiled: November 30, 2006Date of Patent: June 15, 2010Assignee: ASML Netherlands B.V.Inventors: Richard Johannes Franciscus Van Haren, Sami Musa
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Patent number: 7736844Abstract: An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.Type: GrantFiled: July 18, 2007Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Joung Kim, Ji-Yong You, Hyun-Seok Lim
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Publication number: 20100140816Abstract: A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has a larger pitch than the pattern. Finally, one of the two feature types is selectively etched in the open areas. The result is a marker with a large pitch suitable to be read with long wavelength radiation but the edges of the features are defined in an exposure step having a pitch comparable to the product features.Type: ApplicationFiled: November 17, 2009Publication date: June 10, 2010Applicant: ASML NETHERLANDS B.V.Inventors: Richard Johannes Franciscus Van Haren, Maurits Van der Schaar
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Patent number: 7727861Abstract: The invention relates to a method and device that make it possible to increase the productivity of the chip bonding and the before and after working steps associated with the chip bonding. To this end, the invention provides a method for contacting semiconductor chips (3) on a metallic substrate (16), whereby an etch resist (27) is located at least on one substrate side, and semiconductor chips (3) are contacted on the contacting side (30) by means of flip-chip bonding processes, during which a contacting region (7) is created on the contacting side (30) of the substrate (16).Type: GrantFiled: August 28, 2004Date of Patent: June 1, 2010Assignee: Assa Abloy ABInventors: Martin Michalk, Manfred Michalk, Sabine Nieland
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Patent number: 7728945Abstract: A structure for circuit assembly is applied to positional alignment in bonding process. The structure for circuit assembly comprises a first substrate, having a plurality of first terminals and both a first alignment mark and a second alignment mark located in the vicinity of the first terminals, and a second substrate, having a plurality of second terminals and a transmissive area located in the vicinity of second terminals. During the first substrate bonding with the second substrate, as the edge of the transmissive area is located between the first alignment mark and the second alignment mark, and the first alignment mark is outside of the transmissive area, the first terminals are normally connected with the second terminals.Type: GrantFiled: August 17, 2006Date of Patent: June 1, 2010Assignee: Au Optronics Corp.Inventors: Po-Yuan Liu, Chuan-Mau Wei, Chih-Yuan Chien
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Patent number: 7727852Abstract: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning.Type: GrantFiled: August 8, 2008Date of Patent: June 1, 2010Assignee: AU Optronics CorporationInventor: San-Chi Wang
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Patent number: 7723813Abstract: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.Type: GrantFiled: March 18, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Sivananda K. Kanakasabapathy, David W. Abraham
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Patent number: 7719124Abstract: A printed wiring board is disclosed. The printed wiring board includes a board recognition mark formed of a conductive foil, a first component land covered with resist, and a second component land not covered with the resist. The board recognition mark is defined by an area of the conductive foil exposed from a resist opening having the same shape and size as the conductive foil.Type: GrantFiled: November 12, 2007Date of Patent: May 18, 2010Assignee: Ricoh Company, Ltd.Inventor: Hideki Takahashi
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Patent number: 7714387Abstract: A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor film. The pair of source/drain regions is thinner than the remainder of the semiconductor film other than the source/drain regions. The thickness difference between the pair of source/drain regions and the remainder of the semiconductor film is in a range from 10 angstrom (?) to 100 angstrom. The total process steps are reduced and the operation characteristic and reliability of the device are improved.Type: GrantFiled: July 6, 2006Date of Patent: May 11, 2010Assignee: NEC LCD Technologies, Ltd.Inventors: Kunihiro Shiota, Hiroshi Okumura
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Patent number: 7715007Abstract: Alignment of layers during manufacture of a multi-layer sample is controlled by applying optical measurements to a measurement site in the sample. The measurement site includes two diffractive structures located one above the other in two different layers, respectively. The optical measurements include at least two measurements with different polarization states of incident light, each measurement including illuminating the measurement site so as to illuminate one of the diffractive structures through the other. The diffraction properties of the measurement site are indicative of a lateral shift between the diffractive structures. The diffraction properties detected are analyzed for the different polarization states of the incident light to determine an existing lateral shift between the layers.Type: GrantFiled: November 26, 2007Date of Patent: May 11, 2010Assignee: Nova Measuring Instruments, Ltd.Inventors: Boaz Brill, Moshe Finarov, David Schiener
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Patent number: 7709969Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.Type: GrantFiled: May 26, 2006Date of Patent: May 4, 2010Assignee: Sony CorporationInventors: Yuichi Yamamoto, Hayato Iwamoto
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Patent number: 7709355Abstract: There are provided an electronic component production method and an electronic component by which the number of scribing processes can be reduced and the productivity can be made higher while surely preventing short circuiting during the production. An electronic component including a short ring residue portion and a method of producing the electronic component are provided.Type: GrantFiled: May 15, 2008Date of Patent: May 4, 2010Assignee: Canon Kabushiki KaishaInventors: Naohiro Nakane, Kimio Takahashi
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Patent number: 7705477Abstract: An optical target is provided. In one embodiment, the target is formed on a substrate. The target includes a first layer deposited below a second layer on the substrate. The second layer is deposited below a third layer on the substrate. The first layer has a topographic contour formed thereon, the first layer at least partially projecting a patterned topographical contour through the second layer to the third layer.Type: GrantFiled: May 11, 2007Date of Patent: April 27, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Simon Dodd, Michael D. Miller, Joseph M. Torgerson
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Patent number: 7700383Abstract: A manufacturing method for a semiconductor device comprises: mounting a semiconductor element, having an alignment mark, on a substrate; forming a composite of metal film and insulating film such that the surface of the semiconductor element is covered therewith; and removing a part of the composite of metal film and insulating film so as to expose the alignment mark. The position of each electrode of the semiconductor element mounted on the substrate is determined based upon detection results obtained by detection of the exposed alignment mark.Type: GrantFiled: March 17, 2005Date of Patent: April 20, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Yasunori Inoue
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Patent number: 7696060Abstract: A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned at the substrate and the protective layer to expose the substrate. The stack film structure includes an adhesion layer, a stress control layer and a wafer bond alignment mark layer. The adhesion layer is disposed on the protective layer and the exposed substrate. The stress control layer is disposed on the adhesion layer. The wafer bond alignment mark layer is disposed on the stress control layer. The wafer bond alignment mark layer includes an alignment mark at a side of the opening. The cap has a capping portion disposed on the wafer bond alignment mark layer corresponding to the opening.Type: GrantFiled: December 26, 2007Date of Patent: April 13, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jiunn Chen, Meng-Jen Wang
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Patent number: 7692273Abstract: There are provided an electronic component production method and an electronic component by which the number of scribing processes can be reduced and the productivity can be made higher while surely preventing short circuiting during the production. An electronic component including a short ring residue portion and a method of producing the electronic component are provided.Type: GrantFiled: May 31, 2006Date of Patent: April 6, 2010Assignee: Canon Kabushiki KaishaInventors: Naohiro Nakane, Kimio Takahashi
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Patent number: 7692319Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.Type: GrantFiled: September 28, 2006Date of Patent: April 6, 2010Assignee: Ricoh Company, Ltd.Inventor: Koichi Sogawa
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Patent number: 7687925Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.Type: GrantFiled: September 7, 2005Date of Patent: March 30, 2010Assignee: Infineon Technologies AGInventors: Sajan Marokkey, Chandrasekhar Sarma, Alois Gutmann
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Publication number: 20100072635Abstract: A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: September 23, 2008Publication date: March 25, 2010Inventors: Yian-Liang Kuo, Chien-Yi Chen, Yu-Ting Lin, Yung-Sheng Huang