Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Abstract: A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting exposure and development to the spacer formation layer to be patterned and removing the support base; a step of bonding a transparent substrate to a region of the spacer, with which the removed support base made contact, so as to be included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably.

Abstract: A target and method for use in polarized light lithography. A preferred embodiment comprises a first structure located on a reference layer, wherein the first structure is visible through a second layer, and a second structure located on the second layer, wherein the second structure is formed from a photomask containing a plurality of sub-structures oriented in a first orientation, wherein a polarized light is used to pattern the second structure onto the second layer, and wherein a polarization of the polarized light is the same as the orientation of the plurality of sub-structures. The position, size, and shape of the second structure is dependent upon a polarity of the polarized light, permitting a single design for an overlay target to be used with different polarities of polarized light.

Abstract: A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line.

Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).

Abstract: A semiconductor device package includes a semiconductor device, a sealant, a first dielectric layer, an electrically conductive layer, and a second dielectric layer. The semiconductor device includes a contact pad, an active surface, and side surfaces, where the contact pad is disposed adjacent to the active surface. The semiconductor device is formed with a first alignment mark that is disposed adjacent to the active surface. The sealant envelopes the side surfaces of the semiconductor device and exposes the contact pad. The first dielectric layer is disposed adjacent to the sealant and the active surface, and defines a first aperture that exposes the contact pad. The electrically conductive layer is disposed adjacent to the first dielectric layer and is electrically connected to the contact pad through the first aperture. The second dielectric layer is disposed adjacent to the electrically conductive layer.

Abstract: An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Abstract: Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements. Hence the recesses are not detectable by an image recognition apparatus. The size of the metal film, however, is set so that it can be detected by the image recognition apparatus.

Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process.

Abstract: According to one embodiment, a template includes a pattern part which is provided on a substrate and corresponds to a pattern of a semiconductor device, the pattern of the semiconductor device being to be transferred to a wafer, and an alignment mark part which is provided on the substrate, used for positioning of the substrate with respect to the wafer. The alignment mark part has a refractive index that is higher than a refractive index of the substrate.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.

Abstract: A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads.

Abstract: A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first marks and the second marks are different from each other in at least either one of size and geometry.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.

Abstract: A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.

Abstract: Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region. The device feature has a first dimension and the dummy feature has a second dimension, the second dimension being less than a resolution of an alignment mark detector.

Abstract: An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer.

Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.

Abstract: A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

Abstract: Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. Techniques for imaging targets with flexible symmetry characteristics and analyzing the acquired images to determine overlay or alignment error are disclosed.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. An insulating film is formed in the first groove. An interlayer insulating film is formed over the semiconductor substrate. A removing process is performed to remove a part of the interlayer insulating film and a part of the insulating film to form an alignment mark in the first groove.

Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 ?m, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a?) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract: In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area.

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via may be electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other.

Abstract: A film frame aligner for automatically aligning a film frame includes a film frame support, a film frame pusher for pushing the film frame, and a film frame location mechanism for locating at least one notch in the film frame.

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract: An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (?2) exposure steps and N sets of parallel y-directional linear patterns respectively defined by the N exposure steps, and a set of parallel x-directional photoresist bars and a set of parallel y-directional photoresist bars both formed in a lithography process. The N sets of x-directional linear patterns and the set of x-directional photoresist bars are arranged in parallel. The N sets of y-directional linear patterns and the set of y-directional photoresist bars are arranged in parallel.

Abstract: A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction.

Abstract: A method for forming a mark structure on a substrate comprising a plurality of lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines.

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern.

Abstract: A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.

Abstract: An integrated circuit package comprises a package substrate (210, 410), an electrically insulating material (220, 420) adjacent to the package substrate, and a mark (230, 420) on the electrically insulating material. The mark is such that a visual contrast between the mark and the electrically insulating material is maximized when the mark and the electrically insulating material are exposed to coaxial illumination. In one embodiment the electrically insulating material over the package substrate has a first surface roughness and a mark on the solder resist material has a second surface roughness that is no more than approximately twenty times greater than the first surface roughness.

Abstract: A display substrate includes a signal line, a thin-film transistor (“TFT”), a key pattern, a light-blocking pattern, a color filter, a pixel electrode and an alignment key. The signal line and the key pattern are formed on a substrate. The TFT is electrically connected to the signal line. The light-blocking pattern is formed on the substrate and covers the signal line, the TFT and the key pattern. The color filter is formed in a unit pixel area of the substrate. The pixel electrode is formed on the color filter and is electrically connected to the TFT. The alignment key is formed on the light-blocking pattern, and a position of the alignment key on the substrate corresponds to a position of the key pattern on the substrate.

Abstract: The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: An electronic element wafer module is provided, in which a transparent support substrate is disposed facing a plurality of electronic elements formed on a wafer and a plurality of wafer-shaped optical elements are disposed on the transparent support substrate, where a groove is formed along a dicing line between the adjacent electronic elements, penetrating from the optical elements through the transparent support substrate, with a depth reaching a surface of the wafer or with a depth short of the surface of the wafer; and a light shielding material is applied on side surfaces and a bottom surface of the groove or is filled in the groove, and the light shielding material is applied or formed on a peripheral portion of a surface of the optical element, except for on a light opening in a center of the surface.

Abstract: To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 to protect the alignment mark are disposed in an alignment mark forming region 14 of a semiconductor wafer 101 (semiconductor substrate). Each of the protection posts has a diameter (maximum diameter) of, for example, 0.6 ?m. The protection posts 26 are arranged such that the diameter of each of the columnar protection posts 26 is greater than a diameter (for example, 0.2 ?m) of the alignment mark 24. That is, the protection posts 26 are arranged such that the contact area between each of the protection posts 26 and an underlayer thereof (dummy wire layer 22) is greater than the contact area between the alignment mark 24 and an underlayer thereof (dummy wire layer 22).

Abstract: A display device includes first and second substrates, and first and second alignment keys. The first and second substrates have first and second display regions and first and second peripheral regions, respectively. The first alignment key is disposed in the first peripheral region of the first substrate. The first alignment key includes a first pattern and a second pattern. The second alignment key is disposed in the second peripheral region of the second substrate such that the second alignment key faces the first alignment key. As a result, first alignment key may be formed through a procedure of forming the pixel electrode. Therefore, there exists no deviation between the first alignment key and the pixel electrode and the first alignment key may be easily detected because of the first pattern that is opaque, so that misalignment is prevented.

Abstract: A semiconductor apparatus according to the present invention includes one or a plurality of pairs of a standard pattern and an offset pattern formed therein with respect to the standard pattern as manufacturing information and other information at an information writing position, which is visible from the outside, of each semiconductor chip on a wafer.