Abstract: An overlay mark is described, wherein the overlay mark is used for checking the alignment accuracy between a lower layer defined by two exposure steps and a lithography process for defining an upper layer, including a part of the lower layer and a photoresist patter. The part of the lower layer includes two first x-directional, two first y-directional bar-like patterns. The first x-directional and first y-directional bar-like patterns are defined by one exposure step to define a first rectangle. The second x-directional and second y-directional bar-like patterns are defined by another exposure to define a second rectangle, wherein the second rectangle is wider than the first rectangle. The photoresist pattern, which is formed by the lithograph process, is disposed over the part of the lower layer and is surrounded by the bar-like patterns.

Abstract: A misalignment detection device comprising a substrate, at least one integrated circuit (IC), and at least one detection unit is disclosed. The substrate comprises a first positioning pad and a second positioning pad adjacent to the first positioning pad. The integrated circuit is disposed on the substrate and comprises a first positioning bump and a second positioning bump adjacent to the first positioning bump. The first and second positioning bumps substantially correspond to the first and second positioning pads, respectively. The at least one detection unit is electrically coupled to the substrate, wherein the detection unit outputs a fault signal in response to a positioning shift occurring between the first and second positioning pads and the first and second positioning bumps.

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.

Abstract: A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a matrix in a substrate. Portions of the matrix are covered with a mask such that first portions of the matrix are left exposed and second portions of the matrix are covered. Signal response properties of exposed ones of the first structures in the matrix are altered to form a metrology mark. The metrology mark includes first and second mark portions with different signal response properties and which are aligned to a virtual grid. The evaluation of precisely positioned metrology marks may be improved with low impact on process complexity.

Abstract: An electronic element wafer module is provided, in which a transparent support substrate is disposed facing a plurality of electronic elements formed on a wafer and a plurality of wafer-shaped optical elements are disposed on the transparent support substrate, where a groove is formed along a dicing line between the adjacent electronic elements, penetrating from the optical elements through the transparent support substrate, with a depth reaching a surface of the wafer or with a depth short of the surface of the wafer; and a light shielding material is applied on side surfaces and a bottom surface of the groove or is filled in the groove, and the light shielding material is applied or formed on a peripheral portion of a surface of the optical element, except for on a light opening in a center of the surface.

Abstract: An alignment mark on a wafer is described, including at least one dense pattern and at least one block-like pattern adjacent thereto and shown as at least one dark image and at least one bright image adjacent thereto. A method of getting a position reference for a wafer is also described. An above alignment mark is formed. The alignment mark, which is shown as at least one dark image and at least one bright image adjacent thereto that are formed by the at least one dense pattern and the at least one block-like pattern, is then detected.

Abstract: A resist pattern for alignment measurement being shrunk by a heat flow includes a plurality of positive type or negative type line patterns. Widths of spaces between the line patterns are greater than twice those of the line patterns. Alternatively, the resist pattern comprises a box-shaped or slit-shaped measurement pattern and a pair of box-shaped or slit-shaped auxiliary patterns provided inside and outside the measurement pattern, respectively.

Abstract: [Problems] To perform predetermined processing such as annealing and coating application of a semiconductor material with high accuracy on a number of semiconductor formation areas formed over a wide region on a surface of a substrate having elasticity such as a plastic substrate even when the substrate expands and contracts.

Abstract: In order to attain, in a semiconductor device in which a semiconductor element is mounted, formation of a mark of a relatively large size which is easily recognizable by the naked eye or a machine, and which can apply a code system containing enough amount of information for tracing a manufacturing history, a semiconductor device according to the present invention includes an interposer electrically connected to a semiconductor element, which semiconductor device has a mark for displaying at least predetermined information relevant to the semiconductor element.

Abstract: An enhanced technique for determination of an alignment accuracy involves an overlay target assembly which comprises at least two targets, each target having a first sub-structure of a first layer and a second sub-structure of a second layer, wherein, when the first layer and the second layer are correctly aligned, the first sub-structure and the second sub-structure of at least one of the targets are offset with respect to each other by a programmed offset and the overlay target assembly is invariant to at least one geometric transformation. If the offset vectors which describe the offset between the first sub-structure and the second sub-structure all have the same norm, the overlay error may be determined without calibration. Redundancy may be increased by providing each target with two or more programmed offsets between elements of the first sub-structure and elements of the second sub-structure.

Abstract: A method of patterning a substrate according to several steps, including: a) mechanically locating a first masking film over the substrate; and b) segmenting the first masking film into a first masking portion and one or more first opening portions in first locations. Next, mechanically locate a first removal film over the first masking portion and first opening portions. Afterwards, one or more of the first opening portions are adhered to the first removal film. The first removal film and one or more of the first opening portions adhered to the first removal film are mechanically removed to form one or more first openings in the first masking film. Finally, materials are deposited over the substrate through the first openings in the first masking film.

Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.

Abstract: A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: The invention is directed to a mark pattern for forming a process monitor mark in a patterned underlayer to monitor a patterning result of a photoresist layer over the patterned underlayer around the boundary between a peripheral region and a device region of a die, wherein the patterned underlayer is formed by using a first mask having a first pattern in a main region of the first mask and the mark pattern at an unused region of the first mask and the first pattern possesses a first mask critical dimension. The mark pattern comprising: a second pattern and a frame pattern. The second pattern has a second mask critical dimension, wherein the second mask critical dimension is as same as the first mask critical dimension. The frame pattern encloses the second pattern.

Abstract: A integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect.

Abstract: The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the tape and marks a pattern on the second surface of the wafer. There are glue residuals remained in the laser-marking pattern of the die manufactured according to the laser-marking method of the invention, and the components of the glue residuals at least include elements of silicon, carbon and oxygen.

Abstract: Systems and methods for aligning substrates that include microstructures. The microstructures may be electronic or micromechanical components. The system includes a first substrate having a first alignment structure and a second substrate having a second alignment structure. The substrates are positioned so that the first alignment structure contacts the second alignment structure without the substrates directly contacting each other, and one of the substrates is adjusted in relation to the other substrate until the first and second alignment structures lock into place. After alignment, the microstructures on the first substrate and the second substrate may establish a connection with or be positioned in near proximity to each other.

Abstract: A semiconductor device includes: solder balls provided on an upper package; and pads provided on a lower package and directly connected to the solder balls, wherein at least one of the pads serves as a fiducial mark. Further, a shape of at least one of the pads is different from that of other pads and an area of at least one of the pads is substantially equal to that of the other pads.

Abstract: Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Abstract: There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.

Abstract: Disclosed is a semiconductor chip having an alignment mark which is formed on the surface of the semiconductor chip where no external connection bump is formed, and which has the position information of the external connection bump. A method of manufacturing the semiconductor chip having an alignment mark is also provided. Because the semiconductor chip includes the alignment mark having the position information of the external connection bump, the external connection bump is matched with a via which is formed in the external circuit layer of a printed circuit board including the semiconductor chip, thus improving electrical connection with the printed circuit board, and increasing the reliability of the printed circuit board including the semiconductor chip.

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: An alignment mark structure includes a first pair of first side walls and a second pair of second side walls. The first pair of first side walls faces each other and extends in a first direction. The first pair of first side walls crosses a first data detection line. The second pair of second side walls faces each other and extends in a second direction being different from the first direction. The second pair of second side walls crosses the first data detection line.

Abstract: An alignment mark on a substrate includes a periodic structure of a plurality of first elements and a plurality of second elements. The elements are arranged in an alternating repetitive sequence in a first direction. An overall pitch of the periodic structure is equal to a sum of a width of the first element and a width of the second element in the first direction. Each first element has a first periodic sub-structure with a first sub-pitch and each second element has a second periodic sub-structure with second sub-pitch. An optical property of the first element for interaction with a beam of radiation having a wavelength ? is different from the optical property of the second element. The overall pitch is larger than the wavelength ?, and each of the first and the second sub-pitch is smaller than the wavelength.

Abstract: An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion, and a bonding layer is formed to cover the projecting portion. In addition, before the bonding layer is formed, a portion of the semiconductor substrate to be the projecting portion is irradiated with accelerated ions to form a brittle layer. After the bonding layer and the supporting substrate are bonded together, heat treatment for separation of the semiconductor substrate is performed to provide a semiconductor layer over the supporting substrate. The semiconductor layer is selectively etched, and a semiconductor element is formed and a semiconductor device is manufactured.

Abstract: The invention relates to a method for measuring the relative position of a first and a second alignment mark on a substrate. The first alignment mark comprises a periodic structure having a first portion with a first periodicity (PE1) and an adjacent second portion with a second periodicity (PE2). The second alignment mark (11) comprises a periodic structure having a first portion with the second periodicity (PE2) and an adjacent second portion with the first periodicity (PE1). The first and second alignment marks are arranged such that the first portions are substantially located one over the other and the second portions are substantially located one over the other. The method further comprises generating a Moiré pattern from the alignment marks and determining the relative positions of the first and second alignment marks based on the periodicity of the Moiré pattern.

Abstract: To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 to protect the alignment mark are disposed in an alignment mark forming region 14 of a semiconductor wafer 101 (semiconductor substrate). Each of the protection posts has a diameter (maximum diameter) of, for example, 0.6 ?m. The protection posts 26 are arranged such that the diameter of each of the columnar protection posts 26 is greater than a diameter (for example, 0.2 ?m) of the alignment mark 24. That is, the protection posts 26 are arranged such that the contact area between each of the protection posts 26 and an underlayer thereof (dummy wire layer 22) is greater than the contact area between the alignment mark 24 and an underlayer thereof (dummy wire layer 22).

Abstract: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength.

Abstract: A display device includes first and second substrates, and first and second alignment keys. The first and second substrates have first and second display regions and first and second peripheral regions, respectively. The first alignment key is disposed in the first peripheral region of the first substrate. The first alignment key includes a first pattern and a second pattern. The second alignment key is disposed in the second peripheral region of the second substrate such that the second alignment key faces the first alignment key. As a result, first alignment key may be formed through a procedure of forming the pixel electrode. Therefore, there exists no deviation between the first alignment key and the pixel electrode and the first alignment key may be easily detected because of the first pattern that is opaque, so that misalignment is prevented.

Abstract: A method and a system of alignment of an integrated circuit chip pick-and-place equipment with an origin of a wafer supporting these circuits, comprising optically searching on the wafer at least one reference pattern formed, on manufacturing of the integrated circuits, in a reference chip, the reference pattern being different from optically-recognizable patterns of the other chips.

Abstract: A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.

Abstract: An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.

Abstract: A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium.

Abstract: A chip package including a substrate, a chip and a mark is provided. The substrate has a carrying surface. A mark region is disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the substrate. The mark is disposed in the mark region for recording a process parameter.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate and methods for using such overlay mark are disclosed. In one embodiment, the overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark is smoothly joined with a portion outside of the orientation identification mark on the peripheral surface, has a planar surface that is orthogonal to an inner diameter direction of the semiconductor wafer, and has a gloss different from that in the portion outside of the orientation identification mark on the peripheral surface.

Abstract: The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark has a terraced structure that is concave toward an inner diameter direction of the semiconductor wafer with respect to a portion outside of the orientation identification mark on the peripheral surface, and has a planar surface that is orthogonal to a diameter direction of the semiconductor wafer; and has a gloss different from that of the portion outside of the orientation identification mark on the peripheral surface.

Abstract: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes that vary when rotated 360°, such that the microstructures are positioned at a specific orientation in the receptacles.

Abstract: A system that facilitates precise inter-chip alignment. The system includes a first integrated circuit chip, whose surface has etch pit wells. The system also includes a second integrated circuit chip, whose surface has corresponding etch pit wells that mate with the etch pit wells of the first integrated circuit chip. Spherical balls are placed in the etch pit wells of the first integrated circuit chip such that when the corresponding etch pit wells of the second integrated circuit chip are substantially aligned with the spherical balls, the spherical balls mate with the etch well pits of the second integrated circuit chip, thereby precisely aligning the first integrated circuit chip with the second integrated circuit chip.

Abstract: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

Abstract: As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark contrasts strongly with the reflective surface of the substrate in the marking area. As a result, the mark may be read with an optoelectronic imaging system with a higher rate of reliability than marks disposed at a substrate surface having a microtopographical profile with greater variation from a nominal surface plane. An IHS with a mark so disposed provides benefits when include as a portion of an integrated circuit package, which in turn provides benefits when included as a portion of an electronic system.

Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N?-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

Abstract: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures.

Abstract: The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning.

Abstract: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.