Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: An SRAM of the present invention has a first load resistor connected between a first power source terminal and a first node, a second load resistor connected between the first power source terminal and a second node, a first drive transistor having a source-drain path connected between the first node and a second power source terminal, and a gate connected to the second node, a second drive transistor having a source-drain path connected between the second node and the second power source terminal, and a gate connected to the first node, a first switching transistor having a source-drain path connected between the first node and a first bit line, and a gate connected to a word line, and a second switching transistor having a source-drain path connected between the first node and a second bit line, and a gate connected to the word line.

Abstract: The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors.

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: Semiconductor memory devices include a plurality of word line reverse diodes located at alternating ends of a plurality of parallel word lines. A plurality of well bias tapping regions are also located at alternating ends of the plurality of parallel word lines, but at opposite ends of the word lines from the plurality of reverse diodes. A compact semiconductor memory device is thereby provided.

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2.

Abstract: This invention discloses a memory cell having a first polysilicon as a gate. The memory cell includes a three-layer structure covering the first polysilicon as gate with a plurality of via-1 openings exposing the first polysilicon as gate therein wherein the three-layer structure includes a first TEOS oxide layer covered by a silicon nitride layer which is covered by a second TEOS oxide layer. The second TEOS layer includes a resistor portion defined a plurality of trenches therein. The memory cell further includes a patterned second polysilicon layer covered the via-1 openings thus contacting the gate and a connector portion on the second TEOS layer to function as connector therefor. The second polysilicon layer further covering the resistor portion includes the plurality of trenches to function as a load resistor therein whereby the load resistor is prolonged by the trenches.

Abstract: An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N.sup.+ source and drain regions; N.sup.- source and drain regions formed under the N.sup.+ source and drain regions; and P.sup.- impurity regions whose predetermined portion is overlapped with the N.sup.- source and drain region.

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact.

Abstract: Semiconductor elements, such as driving MOS transistors, transfer MOS transistors and the like are formed in a element region defined on the surface of a semiconductor substrate. A first interlayer insulation layer is formed on these surfaces. A grounding wiring layer is formed over substantially entire surface of the first interlayer insulation layer. Also, a silicon nitride layer and a second interlayer insulation layer are formed sequentially on the surface of the grounding wiring layer. Then, a first contact hole reaching a gate electrode of the driving MOS transistor is provided at a desired position. Then, a side wall insulation layer of silicon nitride layer is formed only on the side wall surface of the grounding wiring layer facing the contact hole.

Abstract: A static RAM has a low resistive contact film disposed in direct contact with a storage node of a memory cell and the gate electrode of a driver transistor in a through-hole, and in direct contact with an end portion of a high-resistance load. An accurate and stable resistance can be obtained for the high-resistance load without raising the contact resistance between the storage node and the gate electrode of the driver transistor.

Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.

Abstract: An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pull-down transistors are masked during the oxidation process, the gate electrodes of the load and pull-down transistors have the conventional rectangular shape. The modified shape of the gate electrodes of the pass transistors decreases the current flowing through the pass transistors relative to that which flows through the pull-down transistors, reducing the likelihood that data can inadvertently be lost from the SRAM cell.

Abstract: The semiconductor memory device disclosed includes an element isolation insulating film, a first diffusion layer, a second diffusion layer. The first diffusion layer of a first conductivity type is buried inside the semiconductor substrate, and has an impurity concentration higher than that of the semiconductor substrate. The first diffusion layer is provided at a shallow position in the area where the element isolation insulating film is formed and is provided a deep position in the area where the element isolation insulating film is not formed. The second diffusion layer of a second conductivity type is at an area ranging from the surface of the semiconductor substrate to the first diffusion layer inside the semiconductor substrate. A p-n junction is formed at a junction portion between the first and second diffusion layers. The structure thus configured has a high resistance to soft errors.

Abstract: A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer.

Abstract: A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

Abstract: The invention encompasses integrated circuits and SRAM cells. In one aspect, the invention includes an integrated circuit comprising: a) an electrically insulative pillar extending substantially vertically outward of an underlying layer, the pillar having opposing substantially vertical side surfaces and a top, the pillar being taller than it is wide; b) a resistor comprising a layer of material which extends along both pillar vertical surfaces and over the top of the pillar; c) a first node in electrical connection with the resistor on one side of the insulative pillar; and d) a second node in electrical connection with the resistor on the other side of the insulative pillar.

Abstract: A resistive structure formed on an integrated circuit substrate is disclosed. The structure includes a plurality of resistive elements serially connected. Each resistive element comprises a forward biased semiconductor junction and a reverse biased semiconductor junction. The resistive value of each resistive element can be varied with a preferred range being from about 500 megohms to about 5 gigaohms. In fabrication, the multiple resistive elements are electrically and physically simultaneously formed and are connected in series to obtain higher resistive values. The disclosed resistive structure allows very high resistances to be obtained using very little planar surface area.

Abstract: An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.

Abstract: An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree.

Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.

Abstract: Integrated circuit memory devices having improved supply line connections utilize preexisting semiconductor regions (e.g., N-type well regions) in a semiconductor substrate as interconnect regions between thin polysilicon supply lines and metal supply lines. A semiconductor substrate is provided having a region of first conductivity type semiconductor therein extending to a face thereof. This region of first conductivity type may be formed in a peripheral circuit portion of the substrate. A memory device, such as an SRAM device, is also preferably provided adjacent the face of the substrate, in a memory cell portion of the substrate. The memory device contains at least one polysilicon load element therein having a first resistivity. A polysilicon supply line is also electrically connected in series between the polysilicon load element and the region of first conductivity type.

Abstract: A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.

Abstract: A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: A non-volatile memory device includes a substrate having memory cell and peripheral circuit regions thereof. A non-volatile memory cell gate on a memory cell region of the substrate includes a floating gate on the substrate, a first insulating gate on the floating gate opposite the substrate, and a control gate on the first insulating layer opposite the floating gate. A resistor layer is provided on a peripheral circuit region of the substrate, and the second insulating layer is provided on the resistor layer opposite the substrate. In addition, a capping layer is provided on the second insulating layer opposite the resistor layer wherein a contact hole is defined by the second insulating layer and the capping layer thereby exposing a portion of the resistor layer. Related methods are also discussed.

Abstract: A plurality of silicon insulating films are formed to separate regions to be formed with elements from each other on a silicon semiconductor substrate. Silicon layers are formed by an epitaxially growing method on the regions to be formed with the elements and the silicon insulating film. An MOS transistor is formed on the monocrystalline silicon layer formed on the regions to be formed with the elements of the silicon layer, and the polysilicon layer formed on the silicon insulating film is used as a high resistance element or doped with an impurity as a conductor line.

Abstract: A layout structure for improving a polysilicon load resistor which has a uniform high resistance is disclosed. A polysilicon film is used as the high resistance load element so that the film has a relatively high resistance. However, the resistance of these resistors often varies. This variation can be up to two orders of magnitude. The non-uniform resistance is caused by hydrogen penetration into the polysilicon resistor. The solution of the present is to layout the SRAM cell so that the polysilicon resistor is completely covered by one of these subsequent layers. In the present invention, the polysilicon resistor is partially covered by different layers, such as a subsequent metal layer or polysilicon layer.

Abstract: A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates are controlled by a word line and a complementary word line.

Abstract: A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region.

Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell. In addition, according to the present invention, the field isolation between active regions is not field oxide but blankly ion-implanted silicon substrate. Therefore, SRAM cells can be densely integrated due to the absence of bird's beak encroachment. Since the present invention has more planar topography than the prior art, it is easily adapted to the VLSI process, which is always restricted by the limit of resolution of photolithography, thus increasing the degree of integration.

Abstract: In a memory cell region, there are formed a pair of driver transistors and a pair of access transistors. On an insulating layer covering these transistors, there are formed a pair of high resistances. To cover the high resistances, there is formed an insulating layer. On the insulating layer, there is formed a word line. To cover the word line, there is formed an insulating layer and, on the insulating layer, there are formed a GND wiring and bit lines. Thereby, a semiconductor memory device capable of stabilized operation even when a lowered power source voltage is used can be obtained.

Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.

Abstract: With regard to paired drive transistors, the shape of an active area is (point or line) symmetrical to a channel area in the vicinity of the channel area. With regard to paired transfer transistors, likewise, the shape of a word line is (point or line) symmetrical to the channel area in the vicinity thereof. With this structure, even if a gate electrode (word line) should be misaligned, therefore, the shapes of the channel areas of the paired transistors would become identical, so that there would be no difference between characteristics.

Abstract: A memory cell having an asymmetrical transistor which provides access to a data storage circuit of the memory cell. The asymmetrical transistor exhibits a forward threshold voltage when forward biased and a reverse threshold voltage when reverse biased. The forward threshold voltage is less than the reverse threshold voltage. The asymmetrical transistor is connected such that during write-disturb mode, the asymmetrical transistor is reverse biased to provide a relatively high reverse threshold voltage. This high reverse threshold voltage minimizes subthreshold current leakage during write-disturb mode, thereby reducing the possibility of data corruption. During read mode, the asymmetrical transistor is forward biased to provide a relatively low forward threshold voltage. This low forward threshold voltage maximizes the read voltage applied to the data storage circuit through the asymmetrical transistor, thereby improving the stability of the memory cell.

Abstract: The present invention provides a semiconductor memory device including (a) a substrate, (b) a first MOS transistor acting as a driver, the first MOS transistor being formed on the substrate, (c) a second MOS transistor acting as a load, the second MOS transistor being formed on an insulative layer formed on the substrate, and (d) a gate electrode formed on a gate insulating film above a channel region of the second MOS transistor, the gate electrode comprising a semiconductor layer and a layer composed of metallic compound thereof. The present invention avoids significant reduction of breakdown voltage of a gate electrode in SRAM including a p-channel TFT as a load, even if a gate insulating film of a p-channel TFT is made thin.

Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract: The pull down transistor of a static SRAM semiconductor device is formed with oxide and polysilicon regions formed on a doped silicon substrate. A masking area is formed over the drain side of the polysilicon and the areas of the drain region proximal to the gate in the silicon and oxide layers below. N+ dopant is implanted into the unmasked areas of said substrate about the polysilicon region with the drain doping offset by the resist overlying the proximal portion of the drain region. A spacer is formed by chemical vapor deposition about the polysilicon region. Next an N- implantation follows with the offset provided by the spacers about the polysilicon region.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: In accordance with still another aspect of this invention, a set of cross-coupled inverters provide a bistable flip flop formed on a semiconductor substrate with a pair of FOX regions defining an area on the surface of a substrate. The substrate is composed of a semiconductor material with a pair of buried contact regions in the silicon substrate juxtaposed with the FOX regions. A control gate electrode is formed on a gate oxide layer on the surface of the substrate between the pair of the FOX regions. A source region and drain region are formed in the substrate juxtaposed with the control gate electrode to form a parasitic FET device between the FOX regions, the source region and the drain region and reaching to separate ones of the buried contact regions. An interpolysilicon dielectric layer over the control gate electrode covers the device and the power supply conductor passes over the control gate electrode.

Abstract: A semiconductor memory device and a fabrication method thereof include formation of surplus gates connected to a cell node of a gate edge region, located at a cell node side of a SRAM access transistor, and to the gate of a driving transistor located at the opposite side thereof. The present invention prevents silicon loss of the substrate caused by the formation of a buried contact in the conventional device, secures an operational stability of the memory cell by controlling differently the current flow of an access transistor in accordance with the condition of the cell node (for example, low level or high level), and facilitates an interconnection in the cell since the gate of a side transistor is used as a substitute for another interconnection (for example, a wiring) when realizing a SRAM.

Abstract: A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

Abstract: An outline of an SRAM cell is rectangular. The SRAM cell have nMOS transistors QN1 and QN3 in a nMOS region 13A being on one side of the longitudinal direction, nMOS transistors QN2 and QN4 in a nMOS region 13B being on the opposite side thereof, pMOS transistors QP1 and QP2 in a central region 12, and isolation regions 14A and 14B being between the regions 13A and 12 and between the regions 13B and 12 respectively. The pMOS transistors QP1 and QP2 are on the nMOS transistor QN1 side and on the nMOS transistor QN2 side respectively within the region 12. The direction of bit lines is perpendicular to the longitudinal direction and the word line is parallel to the longitudinal direction. The nMOS transistors QN1, QN4 and the pMOS transistor QP1 are placed on one side of the regions 13A, 13B and 12 respectively in the direction perpendicular to the longitudinal direction, whereas the nMOS transistors QN3 and QN2 and the pMOS transistor QP2 are placed on the opposite side thereof.