Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: A resistive structure formed on an integrated circuit substrate is disclosed. The structure includes a plurality of resistive elements serially connected. Each resistive element comprises a forward biased semiconductor junction and a reverse biased semiconductor junction. The resistive value of each resistive element can be varied with a preferred range being from about 500 megohms to about 5 gigaohms. In fabrication, the multiple resistive elements are electrically and physically simultaneously formed and are connected in series to obtain higher resistive values. The disclosed resistive structure allows very high resistances to be obtained using very little planar surface area.

Abstract: A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.

Abstract: A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.

Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in t

Abstract: Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: SRAM and other integrated circuitry. In one aspect the invention includes an integrated circuit comprising: a) a first electrically insulating material layer having an outer surface; b) an electrically insulative pillar ring extending substantially vertically outward of the first layer, the pillar ring having opposing inner and outer substantially vertical side surfaces; c) an elongated resistor, the resistor comprising a layer of semiconductive material which serpentines over the first layer outer surface and the pillar ring vertical surfaces to form a container shape resistor within the pillar ring; d) an electrically conductive first node in electrical connection with the resistor on the inside of the insulative pillar ring; and e) an electrically conductive second node in electrical connection with the resistor on the outside of the insulative pillar ring.

Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Abstract: An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.

Abstract: A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second re

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating ann

Abstract: A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically.

Abstract: In a semiconductor polycide resistive element having a first region of polysilicon of one conductivity type and second regions of polysilicon of opposite conductivity type, with silicide overlying the polysilicon but not the first region, the edges of the silicide are spaced apart from the boundaries between the opposite conductivity types.

Abstract: In a semiconductor device, an undoped polysilicon layer on the uppermost layer is used as a resistor having a high resistance without any patterning. A metal wiring layer formed on this resistor is connected to a conductive layer formed below the resistor via a contact hole extending through the high resistor device. In addition, by oxidizing an end portion, exposed in the contact hole, of the resistor, an oxide film is interposed between the high resistor device and the metal wiring layer to attain electrical insulation therebetween. In this manner, the resistor is formed of the undoped polysilicon layer by using a multilayered polysilicon structure including the undoped polysilicon layer. Therefore, the integration degree can be increased, and at the same time, a stepped portion accompanying the multilayered silicon structure is relaxed to improve the flatness of the surface and prevent poor step coverage or bridging of an upper wiring layer.

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction.SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Abstract: A radiation resistant random access memory cell which has a coupling circuit between a storage node of a first CMOS pair and a gate node of a second CMOS pair. The coupling circuit is controlled by a word line and provides a first resistive element between the storage node and the body of the coupling circuit and a second resistive element between the gate node and the body of the coupling circuit.

Abstract: A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Abstract: SRAM cells are manufactured with balanced, high-resistance load resistances by having substantially all of dielectric layer directly over the polysilicon load resistor covered by a metal layer. The metal layer protects the polysilicon during subsequent processing which can adversely alter its characteristics.

Abstract: A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Abstract: A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer.

Abstract: A novel thick film resistor configuration and a method for fabricating thick film resistors, by which such resistors can be processed to achieve targeted electrical properties in an as-fired condition. The configuration and method of this invention involve creating a thick film resistor in the form of a series of short resistors whose combined resistance values approximately equal the predetermined resistance value required of the thick film resistor by its hybrid electronic circuit, yet with the use of minimal post-firing trimming. Such a configuration and method enable the production of thick film resistors from the same ink composition but with significantly different aspect ratios, yet which exhibit minimal differences between TCR values. Consequently, thick film resistors configured and fabricated in accordance with this invention are characterized by enhanced production throughput, repeatability, and reliability.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error.

Abstract: A method of for manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a first polysilicon layer on the semiconductor substrate, patterning and etching the first polysilicon layer, formation of an interpolysilicon layer over the first polysilicon layer, patterning and etching an opening through the interpolysilicon layer exposing a contact area on the surface of the first polysilicon layer, forming a dielectric load resistor in the opening upon the contact area on the first polysilicon layer, and formation of a second polysilicon layer on the device over the dielectric load resistor, over the interpolysilicon layer.

Abstract: A semiconductor device includes a pass transistor (28) electrically coupled to a driver transistor (16) by a common drain region (52). The pass transistor (28) includes the pass gate electrode (44) having a polycrystalline silicon layer (68). The driver transistor (16) includes a driver gate electrode (40) having a polycrystalline silicon layer (74). The dopant concentration in polycrystalline silicon layer (74) is greater than the dopant concentration in polycrystalline silicon layer (68). The differential and dopant concentration between the pass gate electrode (44) and the driver gate electrode (40) results in a greater current gain in the driver transistor (16) relative to the pass transistor (28). When incorporated into an SRAM memory cell (10), the driver transistor (16) and the pass transistor (28) provide greater cell stability by improving the immunity of the cell to electrical disturbance through the pass transistor (28).

Abstract: An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

Abstract: A stabilized power supply device includes a substrate and a passive part laminate layered on the substrate. The passive part laminate, shaped as a single flat board, includes a thin charge storage film element. A thin magnetic inductive film element is laminated on the thin charge storage film element. The device also includes an active part incorporated in a flip chip. The flip chip, including semiconductors and bump electrodes, is mounted on an upper surface of the passive part laminate. The upper surface of the passive part laminate includes terminals for connecting the passive part laminate to the bump electrodes. This connection also fixes the active part to the passive part laminate.

Abstract: A semiconductor device capable of stably operating even at a low voltage, includes: a semiconductor substrate having a surface region of a first conductivity type; a conductive film directly formed on a surface of the surface region at an area thereof, the conductive film containing impurities of a second conductivity type opposite to the first conductivity type; an oozed diffusion region of the second conductivity type formed by diffusion of the impurities in the conductive film into the substrate, the oozed diffusion region being formed at an area contiguous to the conductive film in the surface region; a low resistivity region of the second conductivity type extending from an area adjacent to the conductive film in the surface region and overlapping the conductive film; and a DDD structure transistor formed on another region of the surface region, wherein a length of a portion of the low resistivity region overlapping the conductive film is substantially the same as a length of a portion of the deep source

Abstract: A memory cell of an SRAM prevents imbalance between GND potentials of a pair of driver transistors. In the memory cell, the driver transistors Q.sub.1 and Q.sub.2 in a pair have the common source region.

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract: In a semiconductor memory device, an n-well is formed in the memory cell area on the surface of a p-type semiconductor substrate. A p-well is formed on the surface of the n-well, and a memory cell transistor is formed on the surface of the p-well. Another p-well is formed in the peripheral circuit area on the substrate surface, and a peripheral transistor is formed on the surface of the p-well. The p-wells are connected electrically by a conductor layer so that these regions have the same voltage level. The memory cell transistor has its threshold voltage set higher than that of the peripheral transistor. The memory device consumes less power, has less decay of gate oxide film, and is suitable for high-density integration.

Abstract: An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.

Abstract: An SRAM semiconductor device having a parallel connection of two series circuits each having a driver transistor and a load connected in series, a wiring for connecting an interconnection point between the driver transistor and load of each of the two series circuits to a control terminal of the driver transistor of the other of the two series circuits, and a transfer transistor connected to each interconnection point, wherein the driver transistor and transfer transistor each are an insulating gate field effect transistor having a channel region formed on the surface of a semiconductor substrate at a predetermined area, source/drain regions on both sides of the channel region, and an insulated gate above the channel region, and the transfer transistor has a resistor region having an impurity concentration lower than the source/drain regions on both sides of the channel region of the driver transistor, the resistor region being contiguous to the channel region of the transfer transistor.

Abstract: An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.

Abstract: A static RAM memory is arranged into groups of four cells sharing a single active region with a contact to one of the bit lines. The shared active region forms the sources of four access transistors. The group of four cells requires only one pair of bit lines instead of the usual two pairs of bit lines. Thus a pair of bit lines occurs for every two cells rather than for every cell. This increases the bit-line pitch and facilitates design and layout of the sense amps. Since only one of the four cells can drive the bit lines at any time, four word lines are used instead of only two. Each cell has two word lines crossing over it, and the cells in a row alternately connect to one or the other word line. Since word-line drivers and decoders are simpler and easier to lay out than the sense amps, the tighter word-line pitch is acceptable. An unused metal line occurs for every two columns of cells. The bit lines are shielded from this unused metal line by power and ground lines.

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Abstract: Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points.

Abstract: A semiconductor substrate includes a plurality of parallel resistor films connected between a pair of conductor strips. The resistor films and conductor strips are coated with a protective coat. The resistor films are cut one by one by laser trimming to adjust the total resistance value of the plurality of parallel resistor films. The protective coat on the uncut resistors remains unremoved.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

Abstract: A semiconductor device includes a first layer made of a first type semiconductor, a second layer provided on the first layer and made of a second type semiconductor, the second layer including low resistance diffusion parts and high resistance diffusion parts, where the first and second type semiconductors are one and the other of n-type and p-type semiconductors, a third layer provided on the low resistance diffusion parts of the second layer and made of the first semiconductor type, thereby forming a pair of transistors which form a flip-flop and use the high resistance diffusion parts as balanced load resistors, and at least first and second isolations isolating the flip-flop.

Abstract: A semiconductor device is disclosed that can effectively prevent a change in the resistance ratio of polysilicon resistor films when a plasma nitride film is formed above a plurality of polysilicon resistor films. The semiconductor device has metal interconnection layers 5a and 5b formed above polysilicon resistor films 3a and 3b, respectively. The ratio of the overlapping area of the polysilicon resistor film 3a and the metal interconnection layer 5a is set to be substantially equal to that of the polysilicon resistor film 3b and the metal interconnection layer 5b.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: An integrated circuit, illustratively an SRAM, having a low resistance path between an access transistor and a pull down transistor is disclosed. Connection for the cell load to the node between the access transistor and pull down transistor is made outside the defined current path.

Abstract: A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame.

Abstract: A memory cell region is provided with a pair of driver transistors as well as a pair of access transistors. Each of the access transistors is formed of a field effect transistor having a gate electrode layer. An insulating layer is formed over the driver transistors and access transistors, and is provided with contact holes located within the memory cell region and reaching the gate electrode layers. Conductive layers are formed on the insulating layer, and are in contact with the gate electrode layers through the contact holes. Thereby, a memory cell structure of an SRAM has a small planar layout area and thus is suitable to high integration.