Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract: An integrated circuit employs a plurality of functional blocks, such as but not limited to, processors (e.g., cores), and an on-die distributed programmable passive variable resistance memory array configured to provide configuration information for each of the plurality of functional blocks. A corresponding sub-portion of the on-die distributed programmable passive variable resistance memory array is fabricated in layers above each respective plurality of functional blocks. The on-die distributed programmable passive variable resistance memory array is used as either non-volatile prepackage configuration information store, or a non-volatile post-package configuration information store that may allow dynamic changing of hardware configuration of the functional blocks both during normal operation and prior to die packaging. A method for making the same is also disclosed.

Abstract: Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

Abstract: Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more non-ohmic select devices can include at least two tunnel barrier regions formed between a first metal material and a second metal material, and a third metal material formed between each of the respective at least two tunnel barrier regions. The non-ohmic select device is a two terminal select device that supports bi-directional current flow therethrough.

Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.

Abstract: To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the second wiring. The interlayer insulating layer between the first wiring and the second wiring has a hole having a width not greater than that of the first wiring. The resistance change element is in contact with the first wiring and has a lower electrode at the bottom of the hole, a resistance change layer thereon, and an upper electrode thereon. They are formed inside the hole. The first wiring contains copper and the lower electrode contains at least one metal selected from the group consisting of ruthenium, tungsten, cobalt, platinum, gold, rhodium, iridium, and palladium.

Abstract: This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode.

Abstract: A steering device. The steering device includes an n-type impurity region comprising a zinc oxide material and a p-type impurity region comprising a silicon germanium material. A pn junction region formed from the zinc oxide material and the silicon germanium material. The steering device is a serially coupled to a resistive switching device to provide rectification for the resistive switching device to form a non-volatile memory device.

Abstract: A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask to define the word lines. The front end of line (FEOL) memory cell elements are in the same layer as the polysilicon gates. The bit lines and the word lines intersect over the devices, and the memory cell elements are formed at the intersections of the bit lines and the word line.

Abstract: A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.

Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

Abstract: Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same.

Abstract: According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.

Abstract: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) on the front side of the integrated circuit die and passive variable resistance memory on the back side of the integrated circuit die. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the back side of the integrated circuit die is electrically connected to the memory control logic on the front side of the integrated circuit die through at least one through-die vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the front side of the integrated circuit die operatively coupled to the memory control logic.

Abstract: A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.

Abstract: Structures and methods to enhance cycling endurance of BEOL memory elements are disclosed. In some embodiments, a memory element can include a support layer having a smooth and planar upper surface as deposited or as created by additional processing. A first electrode is formed the smooth and planar upper surface. The support layer can be configured to influence the formation of the first electrode to determine a substantially smooth surface of the first electrode. The memory element is formed over the first electrode having the substantially smooth surface, the memory element including one or more layers of an insulating metal oxide (IMO) operative to exchange ions to store a plurality of resistive states. The substantially smooth surface of the first electrode provides for uniform current densities through unit cross-sectional areas of the IMO. The memory element can include one or more layers of a conductive metal oxide (CMO).

Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract: A method for fabricating a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second electrode includes a protrusion extending into the resistance structure. The insulating dielectric material includes a material in which a confined conductive region with a programmable resistance is formable via a conditioning signal.

Abstract: A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8?y?2.0) are stacked together.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: Provided is a method of fabricating a nonvolatile memory device.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.

Abstract: A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer.

Abstract: A method for fabricating a resistance variable memory device, includes: providing a substrate having first contacts and second contacts, where the second contacts do not overlap the first contacts; forming a line pattern over the substrate, the line pattern overlapping a first line and including a stacked structure of a first electrode, a resistor, and a second electrode; forming a first contact hole to expose the second contact; forming an insulating spacer on a sidewall of the first contact hole; forming a third contact to fill the first contact hole having the insulating spacer formed therein; and forming a third electrode over the third contact such that the third electrode overlaps a second line extending in a second direction and is cut open over the first contact, where the first and second contacts are alternately arranged on the second line.

Abstract: A polysilicon film to be a resistor element is formed on a resistor element formation region of a semiconductor substrate while a polysilicon gate and high concentration impurity regions are formed on a transistor formation region. Thereafter, an insulating film is formed on the entire surface of the semiconductor substrate. Then, a photoresist film is formed to cover the transistor formation region, and a conductive impurity is ion-implanted into the polysilicon film. Next, the photoresist film is removed by ashing.

Abstract: A device (10) may include a semiconductor layer section (25) and a memory layer section (45) disposed above the semiconductor layer section (25). The semiconductor layer section (25) may include a processor (12; 412) and input/output block (16; 416), and the memory layer section (45) may include memristive memory (14; 300). A method of forming such device (10), and an apparatus (600) including such device (10) are also disclosed. Other embodiments are described and claimed.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract: A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.

Abstract: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.

Abstract: A phase change random access memory (PCRAM) device and method of manufacturing the same are provided. The PCRAM includes bottom electrode contacts formed on a semiconductor substrate that includes a lower structure, phase-change material patterns in contact with the bottom electrode contacts, respectively, and heat insulating units formed between the phase-change material patterns.

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract: A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bit lines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores “data”. In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data.

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract: Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm.

Abstract: According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

Abstract: A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.