Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

Abstract: According to embodiments of the present invention, a memory component is provided. The memory component includes a storage component comprising a resistance changing material; and an electrical contact coupled to the storage component, wherein the electrical contact comprises silicide, wherein the memory component is free of a metal layer between the storage component and the electrical contact, and wherein the electrical contact is free of a metal layer.

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Abstract: There are provided a micro gas sensor and a method for fabricating the same that comprises a micro heater formed inside a polysilicon membrane by doping impurities into a specific region of the polysilicon membrane positioned under a gas sensing substance, thereby improving thermal structural stability and making it easy to form the gas sensing substance. The micro gas sensor comprises: a micro heater formed by doping impurities into polysilicon vapor-deposited on a substrate on which a first insulating layer is formed; a polysilicon membrane for decreasing a heat loss of the micro heater; a power electrode for supplying power and a temperature measurement electrode for measuring a temperature, positioned at both ends of the micro heater; a second insulating layer formed on the micro heater; a sensing substance formed on the second insulating layer, for sensing a gas; and a sensing electrode for measuring a change in properties of the sensing substance.

Abstract: Semiconductor devices and methods of fabricating a semiconductor device are provided. The method includes forming a conductive region in a substrate and forming a dielectric layer on the substrate including the conductive region. The dielectric layer has an opening that exposes the conductive region. A buffer semiconductor pattern having a single crystalline state is formed on the exposed conductive region. A filling semiconductor pattern is formed in the opening using an epitaxial process that employs the single crystalline buffer semiconductor pattern as a seed layer. Related devices are also provided.

Abstract: A resistive random access memory cell over a substrate includes a memory stack structure and a sidewall spacer. The memory stack structure is over the substrate and includes a first electrode layer, a second electrode layer, and a metal oxide layer between the first electrode layer and the second electrode layer. The metal oxide layer has a sidewall. The sidewall spacer is adjacent to the sidewall and has a composition including silicon, carbon, and nitrogen.

Abstract: Passive devices fabricated on glass substrates, methods of manufacture and design structures are provided. The method includes forming an opaque or semi-opaque layer on at least a first side of a glass substrate. The method further includes forming one or more passive devices on the opaque or semi-opaque layer on a second side of the glass substrate.

Abstract: A magnetoresistive element (and method of fabricating the magnetoresistive element) that includes a free ferromagnetic layer comprising a first reversible magnetization direction directed substantially perpendicular to a film surface, a pinned ferromagnetic layer comprising a second fixed magnetization direction directed substantially perpendicular to the film surface, and a nonmagnetic insulating tunnel barrier layer disposed between the free ferromagnetic layer and the pinned ferromagnetic layer, wherein the free ferromagnetic layer, the tunnel barrier layer, and the pinned ferromagnetic layer have a coherent body-centered cubic (bcc) structure with a (001) plane oriented, and a bidirectional spin-polarized current passing through the coherent structure in a direction perpendicular to the film surface reverses the magnetization direction of the free ferromagnetic layer.

Abstract: A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.

Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer, and a recording layer between the first and second layers, which is capable of a transition between a first state of a low resistance and a second state of a high resistance by flowing a current between the first and second layers. A peripheral portion of the recording layer has a composition different from that of a center portion of the recording layer. The center portion includes two kinds of cation elements. And the center portion is different from the peripheral portion in a ratio of the two kinds of cation elements.

Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

Abstract: Disclosed is a memory device provided with a plurality of memory cells and a lead-out line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed above a substrate (1) and a variable resistance element (10) having a lower electrode (7), an upper electrode (9) that comprises a noble metal, and a variable resistance layer (8) disposed between the lower electrode (7) and the upper electrode (9). The resistance value of the variable resistance layer (8) changes reversibly in response to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The lead-out line (12) is in direct contact with the upper electrodes (9) of the memory cells.

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract: A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.

Abstract: A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

Abstract: An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.

Abstract: Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.

Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.

Abstract: A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.

Abstract: The present disclosure relates to the microelectronics field, and particularly, to a resistive switching memory and a method for manufacturing the same. The memory may comprise a lower electrode, a resistive switching layer, and an upper electrode. The resistive switching layer may have carbon nano-tubes embedded therein. Growth of a conductive filament in the resistive switching layer can be facilitated and controlled under an externally applied bias by a local electric field enhancement effect of the carbon nano-tubes, so as to improve performances and stability of the device. The resistive switching memory according to the present disclosure can have a good resistive switching capability. Further, the operating voltage and the resistance value of the device can be well controlled by controlling the length and position of the carbon nano-tubes in the resistive switching layer.

Abstract: An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.

Abstract: Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Abstract: Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.

Abstract: A method of producing a multilayer structure is provided, wherein the method comprises forming a phase change material layer onto a substrate, forming a protective layer, forming a further layer on the protective layer, patterning the further layer in an first patterning step, patterning the protective layer and the phase change material layer by a second patterning step. In particular, the first patterning step may be an etching step using chemical etchants. Moreover, electrodes may be formed on the substrate before the phase change material layer is formed, e.g. the electrodes may be formed on one level, e.g. may form a planar structure and may not form a vertically structure.

Abstract: According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves.

Abstract: Provided is a resistance element which is, when forming the resistance element including a resistor having a small thickness, less liable to cause disconnection of the resistor. Tip regions of electrodes which are formed by stacking a barrier metal film and an aluminum electrode film are formed so as to be single-layer barrier metal electrodes, and the resistor for electrically connecting the parallel barrier metal electrodes to each other is formed by lift-off.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: A method for controlling a resistive property or conductive property in a resistive element using a gas cluster ion beam (GCIB) is described. In one embodiment, the method may include controlling a resistive switching behavior in a resistive switching random-access memory device using a gas cluster ion beam (GCIB).

Abstract: A variable resistive element configured to reduce a forming voltage while reducing a variation in forming voltage among elements, a method for producing it, and a highly integrated nonvolatile semiconductor memory device provided with the variable resistive element are provided. The variable resistive element includes a resistance change layer (first metal oxide film) and a control layer (second metal oxide film) having contact with a first electrode sandwiched between the first electrode and a second electrode. The control layer includes a metal oxide film having a low work function (4.5 eV or less) and capable of extracting oxygen from the resistance change layer. The first electrode includes a metal having a low work function similar to the above metal, and a material having oxide formation free energy higher than that of an element included in the control layer, to prevent oxygen from being thermally diffused from the control layer.

Abstract: The method of manufacturing a semiconductor memory includes a process of forming a projection by performing an insulator forming process on the exposed side surface of a reactive conductive material and a non-reactive conductive material that are stacked above a substrate so as to change a predetermined length of the side surface of the reactive conductive material into an insulator, and thereby causing the side surface of the non-reactive conductive material to project outward from the side surface of the reactive its conductive material. The insulator forming process is an oxidation process or a nitridation process, the reactive conductive material is a material that reacts chemically and changes into the insulator in the oxidation process or nitridation process, and the non-reactive conductive material is a material that does not change into the insulator in the oxidation process or nitridation process.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, and forming a reversible resistance-switching element coupled to the steering element. The reversible resistance-switching element includes one or more of TiOx, Ta2O5, Nb2O5, Al2O3, HfO2, and V2O5, and the reversible resistance switching element is formed without being etched. Numerous other aspects are provided.

Abstract: A semiconductor memory device according to an embodiment includes: first lines provided on a substrate; second lines provided between the first lines and the substrate so as to intersect the first lines; and a first memory cell array including first memory cells, each of the first memory cells being provided at respective intersections of the first lines and the second lines and including a current rectifying element and a variable resistor connected in series. The variable resistor of the first memory cell includes a first recording layer and a second recording layer, the first recording layer being made of an oxide of a first metal material, the second recording layer being made of the first metal material and being formed so as to contact with the first recording layer. The second recording layer is closer to the first line than the first recording layer is.

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract: A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.

Abstract: A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a stopper film on the memory cell layer. The method of manufacturing a semiconductor storage device also includes: etching the stopper film, the memory cell layer, and the first wiring layer; polishing an interlayer insulating film to the stopper film after burying the stopper film, the memory cell layer, and the first wiring layer with the interlayer insulating film; performing a nitridation process to the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film, respectively; and forming a second wiring layer on the adjustment film, the second wiring layer being electrically connected to the adjustment film.

Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

Abstract: Disclosed are an oxide-based nonvolatile memory with superior resistive switching characteristics and a method for preparing the same. More particularly, the disclosure relates to a nonvolatile memory device having a metal/reduced graphene oxide (r-GO) thin film/metal structure and a method for preparing the same.

Abstract: Three-dimensionally spatially localized artificial filament in the active layer of the memristive device formed by means of ion implantation through the top electrode structure provide the means to achieve high repeatability and high reliability of the memristive devices, leading to significantly improved manufacturing yield. The memristive devices fabricated according to the disclosed method of fabrication can be used in data storage, signal processing and sensing applications.

Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

Abstract: Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

Abstract: Methods of forming diode structures for use in memory cells and memory arrays, such as resistive random access memory (RRAM). The methods include forming a first electrode by chemisorbing a graphite material (e.g., graphene) on a conductive material. A low-k dielectric material may be formed over surfaces of the first electrode exposed through an opening in a dielectric material overlying the first electrode, followed by formation of a high-k dielectric material over the low-k dielectric material. A remaining portion of the opening may be filled with another conductive material to form a second electrode. The first and second electrodes of the resulting diode structure have different work functions and, thus, provide a low thermal budget, a low contact resistance, a high forward-bias current and a low reverse-bias current. A memory cell and a memory array including such a diode structure are also disclosed.

Abstract: A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.

Abstract: A variable resistance nonvolatile memory element (10) is formed from a first electrode (101) comprising a material including a metal as a main component, a variable resistance layer (102) having a reversibly changing resistance value in response to applied predetermined electric pulses having different polarities, a semiconductor layer (103) comprising a material including a nitrogen-deficient silicon nitride as a main component, and a second electrode (104). The variable resistance layer (102) includes a first variable resistance layer (102a) adjacent to the first electrode (101) and a second variable resistance layer (102b), both comprising a material including an oxygen-deficient transition metal oxide as a main component. The first variable resistance layer (102a) has a higher oxygen content atomic percentage than the second variable resistance layer (102b).

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Abstract: Nitrogen-doped MgO insulating layers exhibit voltage controlled resistance states, e.g., a high resistance and a low resistance state. Patterned nano-devices on the 100 nm scale show highly reproducible switching characteristics. The voltage levels at which such devices are switched between the two resistance levels can be systematically lowered by increasing the nitrogen concentration. Similarly, the resistance of the high resistance state can be varied by varying the nitrogen concentration, and decreases by orders of magnitude by varying the nitrogen concentrations by a few percent. On the other hand, the resistance of the low resistance state is nearly insensitive to the nitrogen doping level. The resistance of single Mg50O50-xNx layer devices can be varied over a wide range by limiting the current that can be passed during the SET process. Associated data storage devices can be constructed.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cell holes (101) formed through an interlayer insulating layer (80) at respective cross-points of a plurality of first wires (10) of a stripe shape and a plurality of second wires (20) of a stripe shape when viewed from above such that the memory cell holes (101) expose upper surfaces of the plurality of first wires, respectively, a plurality of dummy holes (111) formed on the plurality of first wires in the interlayer insulating layer such that the dummy holes reach the upper surfaces of the plurality of first wires, respectively, and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode (30) and a variable resistance layer (40); an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening o

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.