Conductive Layer Comprising Transition Metal, E.g., Ti, W, Mo (epo) Patents (Class 257/E21.168)
-
Patent number: 7902065Abstract: A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer.Type: GrantFiled: November 14, 2007Date of Patent: March 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Baek Mann Kim, Seung Jin Yeom, Young Jin Lee, Dong Ha Jung, Jeong Tae Kim
-
Patent number: 7867896Abstract: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.Type: GrantFiled: April 2, 2009Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Wei Cao, Hua Chung, Vincent W. Ku, Ling Chen
-
Patent number: 7851808Abstract: A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer.Type: GrantFiled: October 27, 2008Date of Patent: December 14, 2010Assignee: Samsung LED Co., Ltd.Inventors: Sang-Yeob Song, Ji Hye Shim, Bum Joon Kim
-
Patent number: 7846840Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: GrantFiled: December 22, 2009Date of Patent: December 7, 2010Assignee: Applied Materials, Inc.Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung
-
Patent number: 7799653Abstract: A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer tType: GrantFiled: July 25, 2008Date of Patent: September 21, 2010Assignee: Industrial Technology Research InstituteInventors: Heng-Yuan Lee, Ching-Chiun Wang, Tai-Yuan Wu
-
Patent number: 7786010Abstract: An apparatus and a method form a thin layer on each of multiple semiconductor substrates. A processing chamber of the apparatus includes a boat in which the semiconductor substrates are arranged in a vertical direction. A vaporizer vaporizes a liquid metal precursor into a metal precursor gas. A buffer receives a source gas from the vaporizer and increases a pressure of the source gas to higher than atmospheric pressure, the source gas including the metal precursor gas. A first supply pipe connects the buffer and the processing chamber, the first supply pipe including a first valve for controlling a mass flow rate of the source gas. A second supply pipe connects the vaporizer and a pump for creating a vacuum inside the processing chamber, the second supply pipe including a second valve for exhausting a dummy gas during an idling operation of the vaporizer.Type: GrantFiled: September 18, 2007Date of Patent: August 31, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Wook Lee, Wan-Goo Hwang, Bu-Cheul Lee, Jeong-Soo Suh, Sung-Il Han, Seong-Ju Choi
-
Patent number: 7772114Abstract: Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times.Type: GrantFiled: December 5, 2007Date of Patent: August 10, 2010Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Feng Chen, Karl B. Levy
-
Patent number: 7754604Abstract: The present invention provides improved methods of depositing tungsten-containing films on substrates, particularly on silicon substrates. The methods involve depositing an interfacial or “flash” layer of tungsten on the silicon prior to deposition of tungsten nitride. The tungsten flash layer is typically deposited by a CVD reaction of a tungsten precursor and a reducing agent. According to various embodiments, the tungsten flash layer may be deposited with a high reducing agent to tungsten-precursor ratio and/or at low temperature to reduce attack by the tungsten precursor. In many cases, the substrate is a semiconductor wafer or a partially fabricated semiconductor wafer. Applications include depositing tungsten nitride as (or as part of) a diffusion barrier and/or adhesion layer for tungsten contacts.Type: GrantFiled: February 6, 2006Date of Patent: July 13, 2010Assignee: Novellus Systems, Inc.Inventors: Panya Wongsenakhum, Juwen Gao, Joshua Collins
-
Patent number: 7745348Abstract: A method of manufacturing a semiconductor device employs a PEALD method including using an organometallic Ta precursor to form a TaN thin film. As a result, a conformal TaN diffusion barrier may be formed at a temperature of 250° C. or higher, so that impurities are reduced and density is increased in the TaN thin film.Type: GrantFiled: September 15, 2005Date of Patent: June 29, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Han-Choon Lee
-
Publication number: 20100159694Abstract: Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.Type: ApplicationFiled: March 19, 2009Publication date: June 24, 2010Applicant: Novellus Systems Inc.Inventors: Anand Chandrashekar, Mirko Glass, Raashina Humayun, Michael Danek, Kaihan Ashtiani, Feng Chen, Lana Hiului Chan, Anil Mane
-
Patent number: 7718468Abstract: A method includes (a) preparing a substrate, and (b) growing a ZnO-containing compound semiconductor layer above the substrate by supplying at the same time at least Zn and O as source gases and S as a surfactant.Type: GrantFiled: August 20, 2008Date of Patent: May 18, 2010Assignee: Stanley Electric Co., Ltd.Inventors: Tomofumi Yamamuro, Michihiro Sano, Hiroyuki Kato, Akio Ogawa
-
Patent number: 7718552Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.Type: GrantFiled: April 4, 2006Date of Patent: May 18, 2010Assignee: The Regents of the University of CaliforniaInventors: Zuruzi Abu Samah, Noel C. MacDonald, Marcus Ward, Martin Moskovits, Andrei Kolmakov, Cyrus R. Safinya
-
Patent number: 7713874Abstract: Methods for performing periodic plasma annealing during atomic layer deposition are provided along with structures produced by such methods. The methods include contacting a substrate with a vapor-phase pulse of a metal source chemical and one or more plasma-excited reducing species for a period of time. Periodically, the substrate is contacted with a vapor phase pulse of one or more plasma-excited reducing species for a longer period of time. The steps are repeated until a metal thin film of a desired thickness is formed over the substrate.Type: GrantFiled: May 2, 2007Date of Patent: May 11, 2010Assignee: ASM America, Inc.Inventor: Robert B. Milligan
-
Patent number: 7709376Abstract: A method for fabricating a semiconductor device includes forming a dielectric film on a semiconductor substrate; forming an opening in the dielectric film; forming a refractory metal film in the opening; performing a nitriding process to the refractory metal film; removing a nitride of the refractory metal film formed on a side wall of the opening; and depositing tungsten (W) in the opening from which the nitride is removed.Type: GrantFiled: July 17, 2008Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Matsuyama, Fumio Hoshi
-
Patent number: 7709386Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.Type: GrantFiled: June 17, 2008Date of Patent: May 4, 2010Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Hua Ji, Min-Hwa Chi, Fumitake Mieno
-
Patent number: 7709385Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: GrantFiled: December 16, 2008Date of Patent: May 4, 2010Assignee: Applied Materials, Inc.Inventors: Ming Xi, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
-
Patent number: 7674715Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: GrantFiled: December 16, 2008Date of Patent: March 9, 2010Assignee: Applied Materials, Inc.Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung, Ashok Sinha, Ming Xi
-
Patent number: 7662717Abstract: A method of forming a metal layer on the conductive region of a semiconductor device includes concurrently supplying a mixture gas including a hydrogen gas and a metal chloride compound gas, and a purge gas into a chamber having a sealed space for a predetermined time, thereby forming a first metal layer on the semiconductor substrate, using a plasma enhanced chemical vapor deposition (PECVD) method. The hydrogen gas and metal chloride gases are thereafter alternately supplied for a predetermined time while the purge gas is continuously supplied into the chamber, thereby forming a second metal layer on the first metal layer, using a PECVD method. Deterioration of semiconductor devices due to high heat by a conventional CVD method can be prevented using a PECVD method as a low temperature process, thereby improving a production yield.Type: GrantFiled: April 9, 2008Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Lee, Hyun-Young Kim, Kwang-Jin Moon
-
Patent number: 7648904Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.Type: GrantFiled: June 28, 2007Date of Patent: January 19, 2010Assignee: Hynix Semiconductor Inc.Inventors: Young-Soo Choi, Gyu-Hyun Kim
-
Publication number: 20090321943Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Mark Meldrim, Allen Mcteer, Alain P. Blosse
-
Patent number: 7622375Abstract: Provided are a method of manufacturing an electrically conductive member having excellent properties and such electrically conductive member. A method of manufacturing an electrically conductive member having an electrically conductive film on a surface of a substrate, comprising the steps of: (i) forming a layer containing a colloid on a porous surface of a substrate having at least the porous surface by applying a colloidal solution and (ii) forming an electrically conductive layer by drying the layer containing the colloid.Type: GrantFiled: March 28, 2003Date of Patent: November 24, 2009Assignee: Canon Kabushiki KaishaInventors: Hiroki Kisu, Keiichi Murai, Naotoshi Miyamachi
-
Publication number: 20090233435Abstract: A method is set forth of forming an ohmic electrode having good characteristics on a SiC semiconductor layer. In the method, a Ti-layer and an Al-layer are formed on a surface of the SiC substrate. The SiC substrate having the Ti-layer and the Al-layer is maintained at a temperature that is higher than or equal to a first temperature and lower than a second temperature until all Ti in the Ti-layer has reacted with Al. The first temperature is the minimum temperature of a temperature zone at which the Ti reacts with the Al to form Al3Ti, and the second temperature is the minimum temperature of a temperature zone at which the Al3Ti reacts with SiC to form Ti3SiC2. As a result of this maintaining of temperature step, an Al3Ti-layer is formed on the surface of the SiC substrate. The method also comprises further heating the SiC substrate having the Al3Ti-layer to a temperature that is higher than the second temperature.Type: ApplicationFiled: September 21, 2007Publication date: September 17, 2009Inventors: Akira Kawahashi, Masahiro Sugimoto, Akinori Seki, Masakatsu Maeda, Yasuo Takahashi
-
Patent number: 7582557Abstract: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.Type: GrantFiled: January 13, 2006Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Chen Hua Yu
-
Patent number: 7563717Abstract: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper side of the insulating layer. The second polishing step is performed, after completing the first polishing step, for planarizing the insulating interlayer.Type: GrantFiled: December 28, 2005Date of Patent: July 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Ji Hyung Yune
-
Patent number: 7563730Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.Type: GrantFiled: August 31, 2006Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
-
Patent number: 7550385Abstract: A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where the process cycle includes pulsing the organometallic precursor material into the reaction chamber, pulsing the doping agent into the reaction chamber, and pulsing the plasma into the reaction chamber, such that the organometallic precursor material, the doping agent, and the plasma react at the surface of the substrate to form a metal carbide layer. The process cycles can be repeated and varied to form a graded metal carbide layer.Type: GrantFiled: September 30, 2005Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, Juan E. Dominguez, Kevin P. O'Brien, Steven W. Johnston, John D. Peck, David M. Thompson, David W. Peters
-
Publication number: 20090156004Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: ApplicationFiled: December 16, 2008Publication date: June 18, 2009Inventors: MORIS KORI, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung
-
Publication number: 20090156003Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: ApplicationFiled: December 16, 2008Publication date: June 18, 2009Inventors: MING XI, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
-
Patent number: 7544604Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.Type: GrantFiled: August 31, 2006Date of Patent: June 9, 2009Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
-
Patent number: 7544597Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.Type: GrantFiled: January 17, 2006Date of Patent: June 9, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Sook Park, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Sun-Pil Youn, Dong-Chan Lim, Jae-Hwa Park, Jang-Hee Lee, Woong-Hee Sohn
-
Patent number: 7514358Abstract: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.Type: GrantFiled: September 21, 2005Date of Patent: April 7, 2009Assignee: Applied Materials, Inc.Inventors: Wei Cao, Hua Chung, Vincent Ku, Ling Chen
-
Patent number: 7501344Abstract: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a tungsten precursor to form a first boride-containing layer during a first sequential chemisorption process, and exposing the substrate to the boron-containing compound, the tungsten precursor, and ammonia to form a second boride-containing layer over the first boride-containing layer during a second sequential chemisorption process. In one example, the tungsten precursor contains tungsten hexafluoride and the boron-containing compound contains diborane. In another embodiment, a contact layer is deposited over the second boride-containing layer. The contact layer may contain tungsten and be deposited by a chemical vapor deposition process. Alternatively, the contact layer may contain copper and be deposited by a physical vapor deposition process.Type: GrantFiled: April 24, 2007Date of Patent: March 10, 2009Assignee: Applied Materials, Inc.Inventors: Jeong Soo Byun, Alfred Mak
-
Patent number: 7501343Abstract: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a metal precursor to form a first boride-containing layer during a first sequential chemisorption process and exposing the substrate to the boron-containing compound, the metal precursor, and a second precursor to form a second boride-containing layer on the first boride-containing layer during a second sequential chemisorption process. In one example, the metal precursor contains tungsten hexafluoride and the boron-containing compound contains diborane. In another embodiment, a contact layer is deposited over the second boride-containing layer. The contact layer may contain tungsten and be deposited by a chemical vapor deposition process. Alternatively, the contact layer may contain copper and be deposited by a physical vapor deposition process.Type: GrantFiled: April 24, 2007Date of Patent: March 10, 2009Assignee: Applied Materials, Inc.Inventors: Jeong Soo Byun, Alfred Mak
-
Publication number: 20090026626Abstract: A method for fabricating a semiconductor device includes forming a dielectric film on a semiconductor substrate; forming an opening in the dielectric film; forming a refractory metal film in the opening; performing a nitriding process to the refractory metal film; removing a nitride of the refractory metal film formed on a side wall of the opening; and depositing tungsten (W) in the opening from which the nitride is removed.Type: ApplicationFiled: July 17, 2008Publication date: January 29, 2009Inventors: Hideto MATSUYAMA, Fumio HOSHI
-
Patent number: 7473637Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.Type: GrantFiled: July 20, 2005Date of Patent: January 6, 2009Assignee: Micron Technology, Inc.Inventors: Brenda D Kraus, Eugene P. Marsh
-
Patent number: 7465665Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: GrantFiled: May 15, 2007Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Ming Xi, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
-
Patent number: 7465666Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: GrantFiled: June 21, 2007Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung, Ashok Sinha, Ming Xi
-
Publication number: 20080305629Abstract: In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on the tungsten layer. Some examples provide that the tungsten layer may be deposited by sequentially exposing the substrate to the tungsten precursor and a reducing gas (e.g., diborane or silane) during an atomic layer deposition process. The tungsten layer may have a thickness of about 50 ? or less and tungsten nitride layer may have an electrical resistivity of about 380 ??-cm or less. Other examples provide that a tungsten bulk layer may be deposited on the tungsten nitride layer by a chemical vapor deposition process.Type: ApplicationFiled: August 20, 2008Publication date: December 11, 2008Inventors: Shulin Wang, Ulrich Kroemer, Lee Luo, Aihua Chen, Ming Li
-
Publication number: 20080274610Abstract: Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics.Type: ApplicationFiled: April 30, 2008Publication date: November 6, 2008Inventors: Kyung-In Choi, Gil-Heyun Choi, Hyun-Bae Lee, Jong-Won Hong, Jong-Myeong Lee
-
Patent number: 7446034Abstract: An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.Type: GrantFiled: June 27, 2006Date of Patent: November 4, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsueh Shih, Chen Hua Yu
-
Patent number: 7443032Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.Type: GrantFiled: June 7, 2005Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventors: Gurtej Singh Sandhu, Donald L. Westmoreland
-
Patent number: 7435678Abstract: Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble metal oxide layer on a bottom structure.Type: GrantFiled: August 22, 2005Date of Patent: October 14, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Sang-jun Choi
-
Patent number: 7419898Abstract: A method for forming a gate structure includes forming a gate dielectric layer on a semiconductor substrate and a metal gate conductor on the gate dielectric layer. A cap layer is formed on the metal gate conductor. The method provides for patterning the cap layer, the gate metal layer and the gate dielectric layer to form a capped gate conductor. At least one spacer is formed to cover sidewalls of the metal gate conductor and the cap layer, such that the cap layer and the spacer encloses the metal gate conductor layer therein. At least one self-aligned contact structure formed next to the metal gate conductor on the semiconductor substrate. As such, the cap layer and the spacer separate the self-aligned contact structure from directly contacting the metal gate conductor.Type: GrantFiled: February 10, 2006Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jhon-Jhy Liaw
-
Patent number: 7407876Abstract: A method for processing a substrate for forming TaC and TaCN films having good adhesion to Cu. The method includes disposing the substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, and depositing a TaC or TaCN film on the substrate using the PEALD process. The PEALD process includes (a) exposing the substrate to a first process material containing tantalum, (b) exposing the substrate to a second process material containing a plasma excited reducing agent, (c) repeating steps (a) (b) a predetermined number of times, (d) exposing the substrate to plasma excited Argon, and (e) repeating steps (c) and (d) until the TaC or TaCN film has a desired thickness. Preferably, purging of the process chamber is performed after one or more of the exposing steps.Type: GrantFiled: March 20, 2006Date of Patent: August 5, 2008Assignee: Tokyo Electron LimitedInventor: Tadahiro Ishizaka
-
Patent number: 7358174Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.Type: GrantFiled: April 12, 2005Date of Patent: April 15, 2008Assignee: Amkor Technology, Inc.Inventor: J. Daniel Mis
-
Patent number: 7338900Abstract: A method for forming a tungsten nitride film including a first material gas supply step of supplying a first material gas composed of a tungsten compound gas, a reduction step of supplying a reducing gas, a second material gas supply step of supplying a second material gas composed of a tungsten compound gas, and a nitridation step of supplying a nitriding gas. Since a step of depositing tungsten on a substrate 5, and a step of forming tungsten nitride are performed separately, by varying the flow rate of each gas, the pressure when each gas is supplied, and the supply time, or the number of times each step is performed and the order in which the steps are performed, the quantity of tungsten deposited and the quantity of tungsten nitride formed can be controlled easily.Type: GrantFiled: May 31, 2005Date of Patent: March 4, 2008Assignee: Ulvac Inc.Inventors: Eiichi Mizuno, Narishi Gonohe, Masamichi Harada, Nobuyuki Kato
-
Patent number: 7268078Abstract: A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.Type: GrantFiled: December 9, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Ravi Iyer, Sujit Sharan
-
Patent number: 7253092Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is contacted with water for a period of time less than 120 minutes.Type: GrantFiled: June 24, 2003Date of Patent: August 7, 2007Assignee: NEC Electronics America, Inc.Inventors: Elizabeth A. Dauch, John W. Jacobs
-
Patent number: 7253109Abstract: We have discovered a method of providing a thin, approximately from about 2 ? to about 100 ? thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 ??cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.Type: GrantFiled: February 28, 2005Date of Patent: August 7, 2007Assignee: Applied Materials, Inc.Inventors: Peijun Ding, Zheng Xu, Hong Zhang, Xianmin Tang, Praburam Gopalraja, Suraj Rengarajan, John C. Forster, Jianming Fu, Tony Chiang, Gongda Yao, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara
-
Patent number: 7235485Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.Type: GrantFiled: October 14, 2005Date of Patent: June 26, 2007Assignees: Samsung Electronics Co., Ltd., Infineon Technology North America Corp.Inventors: Jun-keun Kwak, Roland Hampp