Conductive Layer Comprising Transition Metal, E.g., Ti, W, Mo (epo) Patents (Class 257/E21.168)
  • Patent number: 7235482
    Abstract: An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: June 26, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ming Wu, Ming-Hsing Tsai, Ching-Hua Hsieh, Shau-Lin Shue
  • Patent number: 7229924
    Abstract: A semiconductor device structure having a barrier layer comprising a conductive portion and a nonconductive portion is disclosed. The conductive portion includes a metal nitride compound and the nonconductive portion includes a metal oxide, metal oxynitride, metal carbide, or metal carbonitride compound. A method of forming the semiconductor device structure is also disclosed. The method comprises forming a barrier layer over a metallization layer and a dielectric layer in the semiconductor device structure. The barrier layer is formed by depositing a thin, metal layer over the metallization layer and the dielectric layer. The metal layer is exposed to a nitrogen atmosphere and the nitrogen reacts with portions of the metal layer over the metallization layer to form a conductive, metal nitride portion of the barrier layer. Portions of the metal layer over the dielectric layer react with carbon or oxygen in the dielectric layer to produce a nonconductive portion of the barrier layer.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 12, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7226854
    Abstract: Methods of forming metal lines in semiconductor devices are disclosed. One example method may include forming lower metal lines and forming an insulation layer on the lower metal lines; etching said insulation layer to a depth; and depositing a material for upper metal lines on the entire surface of said insulation layer and planarizing the material for the upper metal lines to form said upper metal lines. The example method may also include exposing the lower metal lines by etching said upper metal lines and the insulation layer and depositing a material for contact plugs on the entire surfaces of said upper metal lines and said insulation layer and planarizing the material for said contact plugs to form the contact plugs.
    Type: Grant
    Filed: December 26, 2003
    Date of Patent: June 5, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheolsoo Park
  • Patent number: 7220673
    Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten nucleation layer by sequentially exposing a substrate to a boron-containing gas and a tungsten-containing gas within a processing chamber during an atomic layer deposition process, and forming a tungsten bulk layer on the tungsten nucleation layer by exposing the substrate to a processing gas that contains the tungsten-containing gas and a reactive precursor gas within another processing chamber during a chemical vapor deposition process. In one example, the tungsten nucleation layer is deposited on a dielectric material, such as silicon oxide. In another example, the tungsten nucleation layer is deposited on a barrier material, such as titanium or titanium nitride. Other examples provide that the tungsten nucleation layer and the tungsten bulk layer are deposited in the same processing chamber.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: May 22, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Ming Xi, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
  • Publication number: 20070069401
    Abstract: There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma oxidizing treatment is performed to the aluminum film, whereby an aluminum oxide film is formed by oxidizing the aluminum film, and a silicon oxide film is formed between the polycrystalline semiconductor film and the aluminum oxide film.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 29, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuya Kakehata
  • Patent number: 6723640
    Abstract: The present invention provides a method for forming a contact plug of a semiconductor device capable of preventing an attack to conductive patterns. The method includes the steps of: forming a plurality of conductive patterns on a substrate; forming an insulating layer on top of an entire structure including the plurality of the conductive pattern; forming a contact hole by selectively etching the insulating layer; forming a conductive layer for a contact plug on the entire structure including the contact hole; forming a metal sacrificial layer on the entire structure including the conductive layer; exposing the conductive layer by performing an etchback process to the metal sacrificial layer, wherein the metal sacrificial layer is left on a lower topology area induced by the conductive patterns; and forming plugs, each being isolated by polishing the remained metal sacrificial layer, the conductive layer and the insulating layer through the use of slurry.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 20, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Dong-Sauk Kim, Hyung-Soon Park, Ho-Seok Lee, Sang-Ik Kim