Abstract: Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode.

Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure.

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions on the semiconductor substrate, and contact plugs connected to the source and drain regions. The contact plugs includes first impurity-diffused epitaxial layers that contact with the source and drain regions.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: In a gated diode ESD protection structure, the gate is split into two parts to divide the total reverse voltage between two gate regions.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate, a trench, a buried insulated source electrode arranged in a bottom portion of the trench, a first gate electrode and a second gate electrode arranged in an upper portion of the trench and spaced apart from one another. A surface gate contact extends into the upper portion of the trench and is in physical and electrical contact with the first gate electrode and second gate electrode.

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.

Abstract: A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.

Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.

Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.

Abstract: A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminium nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminium nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminium nitride film is formed firstly and/or lastly.

Abstract: A semiconductor device in a peripheral circuit region includes a semiconductor substrate having a plurality of active areas which are disposed distantly from each other; a gate pattern including at least one gate disposed on the active area; a dummy gate disposed between the active areas and first and second pads; first and second pads connected to both sides of the gate and the dummy gate, respectively; and a first wiring formed so as to be in contact with at least one of the first and second pads.

Abstract: In a semiconductor device, a gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating film. Thick regions of the gate insulating film which are located under both ends of the gate electrode, respectively, have a larger thickness than that of a middle region of the gate insulating film which is located under a middle region of the gate electrode.

Abstract: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. A substrate which includes an insulator layer and an epitaxial layer substantially overlying the insulator layer is provided. At least one bond pad region is formed extending into the epitaxial layer to a surface of the insulator layer. At least one bond pad is fabricated at least partially overlying the at least one bond pad region. At least one imaging component is fabricated at least partially overlying and extending into the epitaxial layer. A passivation layer is fabricated substantially overlying the epitaxial layer, the at least one bond pad, and the at least one imaging component. A handle wafer is bonded to the passivation layer. The at least a portion of the insulator layer and at least a portion of the bond pad region is etched to expose at least a portion of the at least one bond pad.

Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

Abstract: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.

Abstract: Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure.

Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.

Abstract: A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.

Abstract: Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.

Abstract: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract: Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.

Abstract: A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Abstract: A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric.

Abstract: Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.

Abstract: A semiconductor device is fabricated having a stack gate structure where a first gate electrode, a second gate electrode and a gate hard mask are stacked. The stack gate structure secures a contact open margin while reducing a loss of the gate hard mask during a self-aligned contact (SAC) etching process of forming a landing plug contact. An intermediate connection layer is formed in a landing plug contact region between the first gate electrodes. Furthermore, the occurrence of a bridge between a gate and a contact can be prevented while forming the landing plug contact. A conductive material is filled into a gate region including a recess between intermediate connection layers to form the first gate electrode. The second gate electrode and the gate hard mask are formed during a gate-patterning process using a gate mask, even though misalignment occurs between the gate and the contact.

Abstract: A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.

Abstract: A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.