Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: A method of forming a film of lanthanide oxide nanoparticles. In one embodiment of the present invention, the method includes the steps of: (a) providing a first substrate with a conducting surface and a second substrate that is positioned apart from the first substrate, (b) applying a voltage between the first substrate and the second substrate, (c) immersing the first substrate and the second substrate in a solution that comprises a plurality of lanthanide oxide nanoparticles suspended in a non-polar solvent or apolar solvent for a first duration of time effective to form a film of lanthanide oxide nanoparticles on the conducting surface of the first substrate, and (d) after the immersing step, removing the first substrate from the solution and exposing the first substrate to air while maintaining the applied voltage for a second duration of time to dry the film of lanthanide oxide nanoparticles formed on the conducting surface of the first substrate.

Abstract: Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.

Abstract: Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed.

Abstract: A semiconductor device has a first-conductivity-type-channel MOSFET formed on a semiconductor substrate, wherein the first-conductivity-type-channel MOSFET is typically a P-channel MOSFET, and is composed of a gate insulating film and a gate electrode provided over the semiconductor substrate, the gate electrode contains a metal gate electrode provided over the gate insulating film, a metal oxide film provided over the metal gate electrode, and another metal gate electrode provided over metal oxide film.

Abstract: A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.

Abstract: Methods of forming non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.

Abstract: Methods of forming memory devices are provided. The methods may include forming a pre-stacked gate structure including a lower structure and a first polysilicon pattern on the substrate. The methods may also include forming an insulation layer covering the pre-stacked gate structure. The methods may further include forming a trench in the insulation layer by removing a portion of the first polysilicon pattern. The methods may additionally include forming a metal film pattern in the trench on the first polysilicon pattern. The methods may also include forming a first metal silicide pattern by performing a first thermal treatment on the first polysilicon pattern and the metal film pattern. The methods may further include forming a second polysilicon pattern in the trench. The methods may additionally include forming a second metal silicide pattern by performing a second thermal treatment on the second polysilicon pattern and the first metal silicide pattern.

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

Abstract: A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.

Abstract: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.

Abstract: A semiconductor memory element is described, including a substrate including a source region, a drain region, and a channel region, a tunnel oxide over the channel region of the substrate, a charge storage layer over the tunnel oxide, a charge blocking layer over the charge storage layer, and a control gate over the charge blocking layer. The charge blocking layer further includes a first layer including a transition metal oxide, a second layer including a metal silicate, a third layer including the transition metal oxide of the first layer.

Abstract: Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The methods may include forming a pattern on a substrate, forming a capping dielectric layer on the pattern, and thermally processing the substrate. After thermally processing the substrate, the methods may further include forming a diffusion barrier layer by a nitride process that may include supplying nitrogen to the capping dielectric layer. The methods may also include forming an etching stop layer on the diffusion barrier layer, forming an inter-layer dielectric layer on the etching stop layer, and planarizing the inter-layer dielectric layer.

Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

Abstract: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.

Abstract: Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.

Abstract: A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Abstract: A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

Abstract: A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.

Abstract: A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.

Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: A nonvolatile memory element which is provided with a floating gate electrode and a high withstand voltage transistor which is provided with a thick gate insulating film are formed over one substrate without increase in a driving voltage of the nonvolatile memory element. A stacked film of a first insulating film and a second insulating film is formed between an island-like semiconductor region and a floating gate electrode of the nonvolatile memory element and between an island-like semiconductor region and a gate electrode of the transistor. The first insulating film overlapping with the floating gate electrode is removed, and the insulating film between the island-like semiconductor region and the floating gate electrode is formed thinner than the gate insulating film of the transistor.

Abstract: Disclosed is a flash memory device and a method of manufacturing the same. The flash memory device includes a floating gate formed on a semiconductor substrate, a select gate self-aligned on one sidewall of the floating gate, and an ONO pattern interposed between the floating gate and the select gate. A self-aligned split gate structure is formed for an EEPROM tunnel oxide cell flash memory device employing a split gate structure, so that a cell current is constant and the erasing characteristic between cells is uniform, thereby improving the reliability.

Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes the steps of: forming a tunnel insulating film on a semiconductor substrate; forming a floating gate electrode on the tunnel insulating film; and forming a silicon nitride film including a low-density silicon nitride film and a high-density silicon nitride film on the floating gate electrode. The method also includes the steps of: forming an isolation trench thereby to expose the low-density silicon nitride film exposed at least in a portion of a side surface of the isolation trench; forming an isolating insulating film covering an internal surface of the isolation trench; removing the silicon nitride film; and forming an interelectrode insulating film and a control gate electrode both covering the floating gate electrode and the isolating insulating film.

Abstract: According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

Abstract: A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

Abstract: A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region.

Abstract: Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.

Abstract: Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

Abstract: In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.

Abstract: A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic.

Abstract: A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween. The interelectrode insulating film covers whole side portions of the floating gate electrode located in a direction different from a direction in which the word line extends, and the control gate electrode covers the side portions of the floating gate electrode located in the direction different from the direction in which the word line extends.

Abstract: Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: Methods of forming memory devices are provided. The methods may include forming a pre-stacked gate structure including a lower structure and a first polysilicon pattern on the substrate. The methods may also include forming an insulation layer covering the pre-stacked gate structure. The methods may further include forming a trench in the insulation layer by removing a portion of the first polysilicon pattern. The methods may additionally include forming a metal film pattern in the trench on the first polysilicon pattern. The methods may also include forming a first metal silicide pattern by performing a first thermal treatment on the first polysilicon pattern and the metal film pattern. The methods may further include forming a second polysilicon pattern in the trench. The methods may additionally include forming a second metal silicide pattern by performing a second thermal treatment on the second polysilicon pattern and the first metal silicide pattern.

Abstract: Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes first and second memory gates on a substrate; a floating poly between the first and second memory gates; first and second select gates at respective outer sides of the first and second memory gates; an oxide layer between the first memory gate and the first select gate and between the second memory gate and the second select gate; a drain region in the substrate at outer sides of the first and second select gates; a source region in the substrate between the first and second memory gates; and a metal contact on each of the drain region and the source region.

Abstract: A selective oxidation process is performed on a gate electrode in a plasma processing apparatus 100. A wafer W with the gate electrode formed thereon is placed on a susceptor 2 within a chamber 1. Ar gas, H2 gas, and O2 gas are supplied from an Ar gas supply source 17, an H2 gas supply source 18, and an O2 gas supply source 19 in a gas supply system 16 through a gas feed member 15 into the chamber 1. At this time, a flow rate ratio H2/O2 of H2 gas relative to O2 gas is set to be 1.5 or more and 20 or less, preferably to be 4 or more, and more preferably to be 8 or more. Further, the pressure inside the chamber is set to be 3 to 700 Pa, such as 6.7 Pa (50 mTorr).

Abstract: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.

Abstract: In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an first insulating film formed thereon. Further, over the entire main surface of the semiconductor substrate, an second insulating film is deposited so that it covers the pattern of the first insulating film and a gate electrode. The second insulating film is formed by a silicon nitride film formed by a plasma CVD method. The first insulating film is formed by a silicon nitride film formed by a low-pressure CVD method. By the provision of such an first insulating film, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.

Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.

Abstract: A manufacturing method of a semiconductor device, including the steps of: loading into a processing chamber a substrate having a high dielectric gate insulating film and a metal electrode, with a side wall exposed by etching; applying oxidation processing to the substrate by supplying thereto hydrogen-containing gas and oxygen-containing gas excited by plasma, with the substrate heated to a temperature not allowing the high dielectric gate insulating film to be crystallized, in the processing chamber; and unloading the substrate after processing from the processing chamber.

Abstract: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.