Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region.

Abstract: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR type nonvolatile semiconductor memory device can be improved.

Abstract: One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.

Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.

Abstract: There is a method of manufacturing a semiconductor device with a dual gate field effect transistor, the method including a semiconductor body a semiconductor material having a surface with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type opposite to the first conductivity type between the source region and the drain region and with a first gate region separated from the surface of the semiconductor body by a first gate dielectric above the channel region and with a second gate region situated opposite to the first gate region and formed within a recess in an opposite surface of the semiconductor body so as to be separated from the channel region by a second gate dielectric wherein the recess is formed with a local change of the doping of the channel region and by etching starting from the opposite surface of the semiconductor body.

Abstract: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

Abstract: A manufacturing method of a nonvolatile semiconductor memory device including: providing a first insulating film and a silicon film on a semiconductor substrate; providing a fifth insulating film containing silicon and oxygen on the silicon film; providing a second insulating film containing silicon and nitrogen on the fifth insulating film; providing a third insulating film on the second insulating film, the third insulating film is composed of a single-layer insulating film containing oxygen or multiple-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, and relative dielectric constant of the single-layer insulating film and the stacked insulating film being larger than relative dielectric constant of a silicon oxide film; providing a fourth insulating film containing silicon and nitrogen on the third insulating film; and providing a control gate above the fourth insulating film.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control gate constitute a gate stack. A stress is caused in the gate stack, whereby the band gap of the gate dielectric is changed by the stress.

Abstract: Non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.

Abstract: A method for fabricating a nonvolatile memory device includes forming a tunneling insulation layer, a first conductive layer for forming a floating gate, and a hard mask over a substrate. A portion of the hard mask, the first conductive layer, the tunneling insulation layer, and the substrate is etched to form a trench. An isolation structure is formed to fill in the trench. The etched hard mask is removed such that an upper portion of the isolation structure protrudes above the etched first conductive layer. A dielectric layer is formed over the etched first conductive layer. A second conductive layer for forming a control gate is formed over the isolation structure and the dielectric layer. The second conductive layer is polished to align an upper surface of the second conductive layer using an upper surface of the isolation structure.

Abstract: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the trenches. Individual charge storage devices are therefore field coupled with two control gates, one on either side.

Abstract: The semiconductor memory device according to the present invention includes a charge storage layer 26 formed over a semiconductor substrate 10 and including a plurality of particles 16 as charge storage bodies in insulating films 12, 24, and a gate electrode 30 formed over the charge storage layer 26, in which the particles 16 are formed of metal oxide or metal nitride.

Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate. A gate dielectric layer is formed on the semiconductor substrate. A first conductive layer is formed on the gate dielectric layer, wherein the first conductive layer is an in-situ doped conductive layer. A second conductive layer is formed on the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a gate electrode.

Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.

Abstract: A method for manufacturing a flash memory device includes: a) forming a stack gate pattern composed of a tunnel oxide layer, a floating gate, ONO layers, and a control gate on a semiconductor substrate; b) conformably forming a first sidewall oxide layer made of a silicon oxide layer along both sidewalls of the stack gate pattern; c) performing a plasma nitride process for forming a nitride barrier layer in the first sidewall oxide layer; d) forming a sidewall nitride layer on the first sidewall oxide layer; e) conformably forming a second sidewall oxide layer on the sidewall nitride layer; and f) performing an etching process for forming a spacer which includes the first sidewall oxide layer, the nitride barrier layer, the sidewall nitride layer, and the second sidewall oxide layer. The flash memory device prevents data from being lost via the spacer equipped with a nitride barrier layer, resulting in increased reliability of a desired flash memory device.

Abstract: A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.

Abstract: There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.

Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Abstract: A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Abstract: In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack; and removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.

Abstract: A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.

Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates.

Abstract: A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region.

Abstract: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region.

Abstract: The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.

Abstract: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.

Abstract: A method of fabricating a non-volatile memory device includes forming a tunneling layer and a conductive layer on a semiconductor substrate, and patterning the conductive layer, the tunneling layer, and the semiconductor substrate to form a conductive pattern, a tunneling pattern, and a trench in the semiconductor substrate. The method also includes filling the trench with a insulating material, and exposing a partial sidewall of the conductive pattern. The method further includes recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate. The floating gate includes a base portion and a protruding portion having a width smaller than that of the base portion. The method also includes etching the insulating layer to form an isolation layer that exposes the base portion of the floating gate.

Abstract: In a method of fabricating a flash memory device, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is etched to form first contact holes through which junction regions of a cell region are exposed. First contact plugs are formed within the first contact holes. A top surface of the interlayer dielectric layer is etched so that portions of the first contact plugs having the largest width are exposed. The interlayer dielectric layer is etched to form a second contact hole through which a junction region of a peri region is exposed. A second metal layer is formed over the first contact plugs and the interlayer dielectric layer so that the second contact hole is gap-filled. A second contact plug is formed within the second contact hole by removing the second metal layer and the exposed portions of the first contact plugs on the interlayer dielectric layer.

Abstract: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: A method of manufacturing a semiconductor device, comprises forming a gate insulating film on a surface of a semiconductor substrate, forming a first group of at least one strip-like gate electrode and a second group of strip-like gate electrodes on a surface of the gate insulating film, each strip-like gate electrode having a first face contacting the gate insulating film, a second face vertically extending from a long side of the first face and a third face curved and extending between the first and second faces, and a gap between the third faces of the adjacent gate electrode being narrower, at the surface of the gate insulating film, than a gap between the second faces of the adjacent gate electrode, and introducing dopant atoms into the surface of the semiconductor substrate through the gaps between the gate electrodes, thereby forming diffusion layers in the semiconductor substrate.

Abstract: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips.

Abstract: A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps.

Abstract: A method of manufacturing a NAND flash memory device, wherein isolation layers are formed in a semiconductor substrate, and an upper side of each of the isolation layers is made to have a negative profile. A polysilicon layer is formed on the entire surface. At this time, a seam is formed within the polysilicon layer due to the negative profile. A post annealing process is performed in order to make the seam to a void. Accordingly, an electrical interference phenomenon between cells can be reduced and a threshold voltage (Vt) shift value can be lowered.

Abstract: The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region.

Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

Abstract: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

Abstract: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.

Abstract: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate, a gate insulating layer, and a control gate over the tunnel oxide layer. Then, a sidewall oxide layer is formed on a gate region. Next, a fluorine plasma ion implantation process is performed on the sidewall oxide layer. Then, a nitride layer is deposited on the sidewall oxide layer. Next, an etch process is performed to form spacer insulating layers.

Abstract: The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.

Abstract: Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction.

Abstract: Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

Abstract: A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic.

Abstract: Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate dielectric layer. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.