Chemical Cleaning (epo) Patents (Class 257/E21.224)
  • Publication number: 20070218680
    Abstract: The method for fabricating a semiconductor device comprises the step of forming an interconnection trench 38 in an inter-layer insulation film 34, the step of forming an interconnection layer 44 of Cu as the main material in the interconnection trench 38, and the step of performing cloth-rubbing processing of rubbing a cloth 2 containing pure water with ammonia and hydrogen solved in on the surface of the interconnection layer 44 buried in the interconnection trench 38.
    Type: Application
    Filed: June 27, 2006
    Publication date: September 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Tsukasa Itani, Makoto Sasaki
  • Patent number: 7262141
    Abstract: A method for cleaning a semiconductor substrate forming device isolation layers in a predetermined region of a semiconductor substrate to define active regions; etching predetermined areas of the active regions to form a recess channel region and such that sidewalls of the device isolation layers are exposed; and selectively etching a surface of the recess channel region using a predetermined cleaning solution to clean the semiconductor substrate where the recess channel region has been formed.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: August 28, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Ho Ko, Chang-Ki Hong, Sang-Jun Choi, Dong-Gyun Han
  • Patent number: 7208428
    Abstract: A thermal treatment apparatus 1 includes a reaction tube 2 for containing wafers 10 contaminated with organic substances having a heater 12 capable of heating the reaction tube; a first gas supply pipe 13 for carrying oxygen gas into the reaction tube 2; and a second gas supply pipe 14 for carrying hydrogen gas into the reaction tube 2. Oxygen gas and hydrogen gas are supplied through the first gas supply pipe 13 and the second gas supply pipe 14, respectively, into the reaction tube 2, and the heater 12 heats the reaction tube 2 at a temperature capable of activating oxygen gas and hydrogen gas. A combustion reaction occurs in the reaction tube 2 and thereby the organic substances adhering to the wafers 10 are oxidized, decomposed and removed.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: April 24, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Shingo Hishiya, Yoshikazu Furusawa, Teruyuki Hayashi, Misako Saito, Kota Umezawa, Syoichi Sato
  • Publication number: 20070037388
    Abstract: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the absence of any plasma ambient.
    Type: Application
    Filed: May 17, 2006
    Publication date: February 15, 2007
    Inventors: JOERG HOHAGE, MATTHIAS LEHR, VOLKER KAHLERT
  • Patent number: 7157415
    Abstract: A new cleaning chemistry based on a choline compound, such as choline hydroxide, is provided in order to address the problem of dual damascene fabrication. An etch stop inorganic layer at the bottom of a dual damascene structure protects the underlying interconnect of copper and allows a better cleaning. A two step etch process utilizing the etch stop layer is used to achieve the requirements of ULSI manufacturing in a dual damascene structure.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: January 2, 2007
    Assignee: EKC Technology, Inc.
    Inventors: Catherine M. Peyne, David J. Maloney, Shihying Lee, Wai Mun Lee, Leslie W. Arkless
  • Patent number: 7125799
    Abstract: A substrate processing method includes the step of removing carbon from a silicon substrate surface and planarizing the silicon substrate surface from which carbon has been removed.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 24, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shintaro Aoyama, Masanobu Igeta, Hiroshi Shinriki, Tsuyoshi Takahashi
  • Publication number: 20040131783
    Abstract: An apparatus and method for extracting impurities from a layer on a substrate includes decomposing the layer on the substrate to expose impurities and extracting the impurities from the substrate. During the decomposing, reacting material may be supplied to the layer as an aerosol. By detecting and monitoring the volume of discharged material from the decomposing, an end point of decomposing may be determined. Surface tension may be provided to extraction solution during extracting to prevent the extraction solution from separating from a nozzle injecting the extraction solution and from being locally saturated with impurities. A receiving module for receiving various sizes of the wafer may be included.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 8, 2004
    Inventor: Sung-Jae Lee