Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.