Abstract: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.

Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Abstract: In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished.

Abstract: A semiconductor wafer is adapted to support partial wafer processing generally transparently to a facility capable of processing a full wafer. The wafer has provided thereon a plurality of semiconductor dice and a plurality of visible reference features. The reference features are positioned among the dice to support a predetermined partitioning of the wafer into partial wafers. The positioning of the reference features may render each partial wafer uniquely visually distinguishable from every other partial wafer. Each partial wafer may contain at least one of the reference features, with the position of each reference feature identified in accordance with a coordinate system of an electronic wafer map. The positioning of the reference features may provide a visual indication of where to cut the wafer to effect the partitioning.

Abstract: A plasma processing apparatus is provided which includes an inert gas supply route connected to a process gas supply piping which supplies a process gas into a processing chamber in a vacuum vessel, a valve which opens or closes the inert gas supply route, and an adjuster which adjusts a flow rate of the inert gas. When processing of a sample is complete, an inert gas is supplied into the process gas supply piping so that a pressure in the process gas supply piping is maintained at a pressure higher than a pressure at which a compound of the process gas and a material of an inner wall of the process gas supply piping vaporizes.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment an integrated circuit feature is formed overlying a semiconductor substrate. A layer of low dielectric constant insulator is deposited overlying the circuit feature and is subjected to a plasma environment. Properties of the low dielectric constant material are measured by scatterometry. The low dielectric constant material is heated to drive off adsorbed water and then the properties of the material are remeasured by scatterometry. The results of the measuring and the remeasuring are compared to determine whether the low dielectric constant material was damaged by the plasma environment.

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The edge band extends at least one half inch from an outer edge of the showerhead up to one fourth of the diameter of the wafer. A process of forming an integrated circuit by forming a silicon dioxide layer on a wafer containing the integrated circuit using the dielectric deposition tool. The silicon dioxide layer is thicker under the edge band than under the central region. A subsequent CMP operation reduces the thickness difference between the wafer outer annulus and the wafer core by at least half. The silicon dioxide layer has a compressive stress between 125 and 225 MPa.

Abstract: A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.

Abstract: Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.

Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Abstract: A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Abstract: Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices.

Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.

Abstract: A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber.

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

Abstract: A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.

Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

Abstract: In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.

Abstract: A method for producing a semiconductor optical device, includes the steps of: (a) forming a semiconductor region on a substrate, the substrate including first and second areas; the first area including device sections (b) forming a first mask on the semiconductor region, the first mask including first patterns periodically arranged in the first area and a second pattern provided in the second area; (c) forming a plurality of periodic structures in each of the device sections and a monitoring structure in the second area by using the first mask, the periodic structures respectively corresponding to the first patterns, the monitoring structure corresponding to the second pattern; (d) measuring a shape of the monitoring structure; (e) selecting a desired periodic structure from the plurality of periodic structures on a basis of a result of measuring the shape of the monitoring structure; (f) forming a second mask including a pattern on the desired periodic structure; and (g) forming stripe mesas including the de

Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.

Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.

Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include forming a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a second insulating layer, a transparent material and a phosphor layer. The transparent material is formed on the first major surface of a semiconductor layer selected from the plurality of semiconductor layers on the basis of an emission spectrum of a light obtained from the first major surface side. The transparent material transmits the light. The phosphor layer is formed on the transparent material and the first major surface of the plurality of the semiconductor layers.

Abstract: A method of manufacturing a nano device by directly printing a plurality of NW devices in a desired shape on a predesigned gate substrate. The method includes preparing an NW solution, preparing a building block for performing decaling onto the substrate by carrying an NW device, forming the NW device by connecting electrodes of each of building block units of the building block using NWs by dropping the NW solution between the electrodes and then through dielectrophoresis, visually inspecting the numbers of NW bridges that are formed between the electrodes of each of the building block units through the dielectrophoresis, grouping the building block units according to the numbers, and decaling the NW device formed on each of the building block units onto the gate substrate by bringing the grouped building block units into contact with the predesigned gate substrate and then detaching the grouped building block units.

Abstract: A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip.

Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract: An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.

Abstract: Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.

Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers corresponds to a section of the optoelectronic device. A plurality of pad areas is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact. The optoelectronic device includes a bad section, wherein the bad section is associated with a compromised metal finger and a compromised pad area. A dielectric spot coating is disposed above the compromised pad area to electrically isolate the bad section.

Abstract: Provided is a method of manufacturing a TFT substrate for preventing characteristics of a native oxide layer in a boundary between a microcrystal semiconductor layer and an amorphous semiconductor layer from being degraded. The method includes forming a gate electrode, forming a gate insulating film, modifying the formed first amorphous silicon thin film into a first crystalline silicon thin film, removing a silicon oxide layer on the surface of the first crystalline silicon thin film, forming the second amorphous silicon thin film, and dry etching the first crystalline silicon thin film and the second amorphous silicon thin film, and it is determined whether or not the in-process TFT substrate after the dry etching is returned to the processes after the dry etching by measuring the emission intensity of radicals in plasma during the dry etching and detecting the presence or absence of the silicon oxide layer in the boundary.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device.

Abstract: A method of fabricating group-III nitride semiconductor laser device includes: preparing a substrate comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, where the laser structure includes a semiconductor region and the substrate, where the semiconductor region is formed on the semipolar principal surface; scribing a first surface of the substrate product in a direction of an a-axis of the hexagonal group-III nitride semiconductor to form first and second scribed grooves; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.

Abstract: An embodiment of the invention provides a laser annealing method, including the steps of radiating a laser beam to an amorphous film on a substrate while scanning the laser beam for the amorphous film, crystallizing the amorphous film, detecting a light quantity of laser beam reflected from the substrate and a scanning speed of the laser beam while the radiation and the scanning of the laser beam are carried out for the amorphous film, and controlling a radiation level and the scanning speed of the laser beam based on results of comparison of the light quantity of laser beam reflected from the substrate, and the scanning speed of the laser beam with respective preset references.

Abstract: A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod.

Abstract: A method for processing a plurality of semiconductor wafers includes acquiring a process parameter measurement for each of the semiconductor wafers, associating each of the semiconductor wafers with one of a plurality of groups based on a respective process parameter measurement for each of the semiconductor wafers, where each respective group corresponds to a respective recipe, and for each one of the groups, processing ones of the semiconductor wafers associated with that group together according to a respective recipe.

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: An example embodiment relates to a method of manufacturing an array of electric devices that includes attaching a platform including a micro-channel structure to a substrate. The method includes injecting first and second solutions into the micro-channel structure to form at least three liquid film columns, where the first and second solutions include different solvent composition ratios and the liquid columns each, respectfully, include different solvent composition ratios. The method further includes detaching the platform the substrate, removing solvent from the liquid film columns to form thin film columns, and treating the thin film columns under different conditions along a length direction of the thin film columns. The solvent is removed from the thin film columns and the thin film columns are treated under different conditions along a length direction of the thin film columns.

Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Abstract: A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.

Abstract: The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.