Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Abstract: A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface.

Abstract: An apparatus and method for monitoring precursor flux is disclosed herein. The apparatus comprises an optical cell configured for electromagnetic radiation spectroscopy and has a precursor reservoir or deposition chamber configured to provide a flow of a vapor deposition precursor therethrough, a first inner window sealing a first optical opening in the precursor reservoir or deposition chamber, a first outer window in optical communication with the first inner window, a first vacuum chamber disposed between the first inner window and the first outer window, a second inner window sealing a second optical opening in the precursor reservoir or deposition chamber, a second outer window in optical communication with the second inner window, a second vacuum chamber disposed between the second inner window and the second outer window. Each window being disposed to be in optical communication with one another, a electromagnetic radiation or light source, and an optical detector.

Abstract: Some embodiments include methods for quality testing material removal procedures. A test structure is formed to contain a pair of electrically conductive segments. The segments are the same relative to a detectable property as long as they are electrically connected, but becoming different relative to such property if they are disconnected from one another. A material is formed over the test structure, and across a region of a semiconductor substrate proximate to the test structure. The material is subjected to a procedure which removes at least some of it, and which fabricates a structure of an integrated circuit construction in the region proximate to the test structure. After the procedure, it is determined if the segments are the same relative to the detectable property.

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device, in which shape variations of discharge electrodes can be early detected so as to prevent a film having a non-uniform thickness from being formed on a substrate. The substrate processing apparatus includes a process chamber configured to stack a plurality of substrates therein, a gas supply unit configured to supply gas to an inside of the process chamber, at least one pair of electrodes installed in the process chamber and configured to receive high-frequency power to generate plasma that excites the gas supplied to the inside of the process chamber, and a monitoring system configured to monitor a shape variation of the electrodes.

Abstract: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: A method of manufacturing a nano device by directly printing a plurality of NW devices in a desired shape on a predesigned gate substrate. The method includes preparing an NW solution, preparing a building block for performing decaling onto the substrate by carrying an NW device, forming the NW device by connecting electrodes of each of building block units of the building block using NWs by dropping the NW solution between the electrodes and then through dielectrophoresis, visually inspecting the numbers of NW bridges that are formed between the electrodes of each of the building block units through the dielectrophoresis, grouping the building block units according to the numbers, and decaling the NW device formed on each of the building block units onto the gate substrate by bringing the grouped building block units into contact with the predesigned gate substrate and then detaching the grouped building block units.

Abstract: A method of manufacturing semiconductor-based light-emitting devices, such as light-emitting diodes (LEDs), is described. The method comprises irradiating an interface region with a gas cluster ion beam (GCIB) to improve the interface region between a light-emitting device stack and the substrate, within the light-emitting device stack, and/or between the light-emitting device stack and a metal contact layer in an end-type contact.

Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.

Abstract: The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory.

Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.

Abstract: In a packaging method of semiconductor device, firstly, a wafer including a number of dies is provided. The wafer has an active surface and a back surface. The active surface adheres to a carrier. Subsequently, a number of openings are formed in each of the dies. Then, an insulating layer is formed on the back surface and on the side walls of the openings. A metal layer is formed to cover the insulating layer and the bottoms of the openings. A pattern protective layer is formed to cover the metal layer and to expose the metal layer outside the openings. Afterwards, the carrier is removed and the wafer is sawed. Later, a transparent substrate having a number of package units is provided. A spacer is formed at peripheral of each of the package units. A number of good dies are choose from the dies and disposed on the spacer.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: Methods and devices for etching a device precursor are provided. For example, a method includes: providing a substrate, determining a temperature associated with the substrate, and etching a metal oxide layer of the substrate, wherein the etching is controlled based on the determined temperature.

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract: Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed.

Abstract: A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. In one embodiment, the showerhead includes a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels.

Abstract: In accordance with one embodiment of the present disclosure, a process of manufacturing a semiconductor laser diode comprising a gain section, a QWI output window, and QWI waveguide areas is provided. The QWI waveguide areas are fabricated using quantum well intermixing and define a QWI waveguide portion in the QWI output window of the laser diode. The QWI output window is transparent to the lasing wavelength ?L. The QWI waveguide portion in the QWI output window is characterized by an energy bandgap that is larger than an energy bandgap of the gain section such that the band gap wavelength ?QWI in the QWI waveguide portion and the QWI output window is shorter than the lasing wavelength ?L. The QWI output window is characterized by a photoluminescent wavelength ?PL. The manufacturing process comprises a ?PL screening protocol that determines laser diode reliability based on a comparison of the lasing wavelength ?L and the photoluminescent wavelength ?PL of the QWI output window.

Abstract: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns (1240) surrounding contacts (1215), said patterns (1240) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (1215). Current flows through active regions (1260) associated with said contacts (1215) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

Abstract: A sensor for selectively determining the presence and measuring the amount of hydrogen in the vicinity of the sensor. The sensor comprises a MEMS device coated with a nanostructured thin film of indium oxide doped tin oxide with an over layer of nanostructured barium cerate with platinum catalyst nanoparticles. Initial exposure to a UV light source, at room temperature, causes burning of organic residues present on the sensor surface and provides a clean surface for sensing hydrogen at room temperature. A giant room temperature hydrogen sensitivity is observed after making the UV source off. The hydrogen sensor of the invention can be usefully employed for the detection of hydrogen in an environment susceptible to the incursion or generation of hydrogen and may be conveniently used at room temperature.

Abstract: A method for producing a substrate including a step of thinning the thickness of the substrate is disclosed. The method is characterized in that it includes the following steps: the formation of a porous zone in an inner layer of the substrate; the progressive thinning of the thickness of the substrate towards the inner layer including a porous zone; the completion of the progressive thinning by polishing; and a controlled stoppage of polishing upon detection of the porous zone.

Abstract: In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.

Abstract: Embodiments of the present invention provide an LED having a Wavelength Shift Layer (WSL) and method of manufacture. Specifically, under embodiment of the present invention, a WSL layer is applied over an LED chip. The WSL itself typically comprises two layers: an adhesion layer applied over a set (at least one) of LED chips, and a conformal coating over the adhesion layer. The adhesion layer provides improved adhesive effect of the conformal coating to the LED chip(s). The conformal coating is comprised of a particular phosphor ratio that is determined based on a wavelength measurement of the underlying LED chip(s). Specifically, under the present invention, a wavelength of a light output by an LED chip(s) (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Typically, the phosphor ratio of is comprised of at least one of the following colors: yellow, green, or red. Regardless, this conformal coating is applied over a glue layer that itself is applied over the LED chip.

Abstract: A method for manufacturing an electronic circuit in three-dimensional space provides for interconnecting electronic components within the circuit by directly writing conducting lines. The method may include observing a direct writing tool of a direct write system using a vision system, determining proper placement of the direct writing tool at least partially based on the step of observing, and directly writing conducting lines in three dimensions using the proper placement. The direct writing may be on a surface or in free space. The method may include stacking a plurality of chips to provide a stack having a top surface and edges extending away from the top and interconnecting connections of the chips by directly writing conducting lines along one of the edges.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.

Abstract: A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The method includes positioning at least one non-invasive sensor on an outer surface of a system component of the processing system, where the at least one invasive sensor forms a wireless sensor network, acquiring a sensor signal from the at least one non-invasive sensor, where the sensor signal tracks a gradual or abrupt change in a processing state of the system component during flow of a process gas in contact with the system component, and extracting the sensor signal from the wireless sensor network to store and process the sensor signal. In one embodiment, the non-invasive sensor can be an accelerometer sensor and the wireless sensor network can be motes-based.

Abstract: A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating.

Abstract: The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.

Abstract: A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF.

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.

Abstract: A stage onto which is electrostatically attracted a substrate to be processed in a substrate processing apparatus, which enables the semiconductor device yield to be improved. A temperature measuring apparatus 200 measures a temperature of the substrate to be processed. A temperature control unit 400 carries out temperature adjustment on the substrate to be processed such as to become equal to a target temperature based on a preset parameter. A temperature control unit 400 controls the temperature of the substrate to be processed by controlling the temperature adjustment by the temperature control unit 400 based on a measured temperature measured by the temperature measuring apparatus 200.

Abstract: A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength.

Abstract: A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters.

Abstract: Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: An optical property evaluation apparatus includes: a light conversion filter converting light emitted from an LED chip or a bare LED package, which is to be evaluated, into a different wavelength of light, and emitting a specific color of light; and an optical property measurement unit receiving the specific color of light emitted from the light conversion filter and measuring the optical properties of the received light.

Abstract: Disclosed is a method (300) of manufacturing at least one semiconductor photovoltaic cell or module and for classifying semiconductor material. In one implementation (500) the method involves luminescence imaging a wafer at each of a plurality of stages (312-324) of the manufacturing process, and comparing at least two images obtained from the imaging step in respect of the same wafer to identify the incidence or growth of a manufacturing process induced fault. The wafer is removed (351-356) from the manufacturing process (310) where a process induced fault is identified that exceeds a predetermined level of acceptability or the fault may be remedied, or the wafer passed to an alternate manufacturing process to match its characteristics. In an alternate implementation the method comprises classifying semiconductor material.

Abstract: A semiconductor device is described that comprises an integrated circuit substrate comprising a plurality of bonding pads for enabling electrical connectivity to a chip circuit. The bonding pads are at least partially covered by a passivation layer having pre-manufactured holes. The device also includes a chip having a plurality of bumps atop the bonding pads, wherein areas of the bumps are larger than respective areas of cooperating holes in the passivation layer.

Abstract: The invention aims to provide substrate treatment equipment that can automatically collect a substrate in a normal condition without needing manual operation. The equipment includes a substrate holder for holding substrates in a multistage manner and a substrate transfer unit for transferring the substrates into the substrate holder, wherein a substrate holding condition of the substrate holder is sensed by a sensing section. The sensing section has photo-sensors, and sensing waveforms sensed by the photo-sensors are compared with a normal waveform. A control section is provided, which controls a substrate transfer unit such that substrates other than at least a substrate that was determined to be abnormal are transferred by the unit.

Abstract: The present invention provides an LED and method of manufacture in which white light is produced. Specifically, under the present invention, a wavelength of a light output by an LED (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Based on the wavelength measurement, a conformal coating is applied to the LED. The conformal coating has a phosphor ratio that is based on the wavelength. Moreover, the phosphor ratio is comprised of at least one of the following colors: yellow, green, or red. The light output of the LED is then converted to white light using the conformal coating. In a typical embodiment, these steps are performed at the wafer level so that uniformity and consistency in results can be better obtained. However, it should be understood that the same teachings could be applied at the chip level. Moreover, several different approaches can be implemented for isolating the coating area. Examples include the use of a paraffin wax, a silk screen, or a photo resist.

Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.

Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.

Abstract: An imaging module includes an imaging chip including a micro-lens guiding incident light and an imaging element in a semiconductor substrate and converting the incident light into an electric signal, and a polarizing glass chip including a polarizing filter glass having a polarizer determining a polarization direction of the incident light arranged on a transparent substrate such that the polarizer faces the micro-lens and a spacer member connected to the polarizing filter glass to adjust a gap between the polarizer and the micro-lens of the imaging chip. In the imaging module, a melt-bonding surface of the spacer member is melt-bonded to the semiconductor substrate such that the polarizer of the polarizing glass chip and the micro-lens of the imaging chip are arranged close to each other via the gap, and the imaging element and the micro-lens of the imaging chip are sealed by the polarizing glass chip.