Abstract: A method of photoluminence (PL) imaging of a series of silicon wafers, the method including the step of: utilizing incident illumination of a wavelength greater than 808 nm. The present invention further provides a method of analysing silicon semiconductor material utilising various illumination, camera and filter combinations. In some embodiments the PL response is captured by a MOSIR camera. In another embodiment a camera is used to capture the entire PL response and a long pass filter is applied to block a portion of the signal reaching the camera/detector.

Abstract: Provided are novel methods of fabricating photovoltaic modules using thermoplastic materials to support wire networks to surfaces of photovoltaic cells. A thermoplastic material goes through a molten state during module fabrication to distribute the material near the wire-cell surface interface. In certain embodiments, a thermoplastic material is provided as a melt and coated over a cell surface, with a wire network positioned over this surface. In other embodiments, a thermoplastic material is provided as a part of an interconnect assembly together with a wire network and is melted during one of the later operations. In certain embodiments, a thermoplastic material is provided as a shell over individual wires of the wire network. A thermoplastic material is then solidified, at which point it may be relied on to support the interconnect assembly with respect to the cell. Also provided are novel photovoltaic module structures that include thermoplastic materials used for support.

Abstract: Provided is a method and system for controlling a fabrication cluster for processing of a substrate in an etch process, the fabrication cluster having equipment settings and process parameters. A correlation of etch stage measurements to actual etch stage data is developed, the etch stage measurements comprising measurements using two or more optical metrology devices and an etch sensor device. An etch stage value is extracted using the developed correlation and the etch stage measurement. If the etch stage measurement objectives are not met, the metrology devices are modified, a different etch sensor device is selected, the etch stage measurements are enhanced, and/or the correlation algorithm is refined. The steps are iterated until the etch stage measurement objectives are met. The extracted etch stage value is used to adjust an equipment setting and/or process parameter of the fabrication cluster.

Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.

Abstract: A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.

Abstract: There is provided a method for inspecting a substrate including: irradiating an illumination light onto a first surface or a second surface opposite to the first surface, of a substrate in which a pattern having a periodicity and extending from the first surface to an inside of the substrate is formed in the first surface, the illumination light having a permeability to permeate the substrate to a predetermined depth; detecting a light reflected from or transmitted through the substrate due to irradiation of the illumination light; and inspecting the substrate by utilizing information based on the periodicity of the pattern obtained from detection of the light reflected from or transmitted through the substrate.

Abstract: A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching.

Abstract: A field effect transistor including a gate insulation portion, an organic semiconductor portion, a source electrode and a drain electrode, wherein when a voltage is applied to the gate at 70° C. for 5.0±0.1 hours so that the field strength in the gate insulation portion would be 100±5 MV/m, the change in the threshold voltage is within 5 V. The organic semiconductor portion has a high driving stability, of which the change in characteristics by driving is thereby small.

Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.

Abstract: A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition.

Abstract: According to one embodiment, a semiconductor device includes a device portion, a first electrode portion, a second electrode portion and a protruding portion. The device portion is provided on a substrate. The first electrode portion is provided on the device portion and is electrically contacted with the device portion. The second electrode portion is provided on the device portion separated from the first electrode portion, and electrically contacted with the device portion. The protruding portion is provided on the device portion and protrudes outward from a peripheral portion of the first electrode portion and the second electrode portion.

Abstract: Provided is a method for designing an etch stage measurement system involving an etch process for one or more layers on a substrate using an etch process tool. The etch process tool uses two or more metrology devices, at least one etch process sensor device, and a metrology processor, the etch stage measurement system configured to meet two or more etch stage measurement objectives. A correlation algorithm using the etch stage measurements to the actual etch stage data is developed and used to extract etch measurement value. If the set two or more etch stage measurement objectives are not met, the optical metrology devices are modified, a different etch process sensor device is selected, the correlation algorithm is refined, and/or the measurement data is enhanced by adjusting for noise.

Abstract: Provided is a system for measuring an etch stage of an etch process involving one or more layers in a substrate, the etch stage measurement system configured to meet two or more etch stage measurement objectives. The system includes an etch process tool, the etch process tool having an etch chamber, a controller, and process parameters. The etch process tool is coupled to two or more optical metrology devices and at least one etch sensor device measuring an etch process parameter with high correlation to the etch stage. The processor is coupled to the etch process tool and is configured to extract an etch measurement value using a correlation of etch stage measurements to actual etch stage data and etch stage measurement obtained from the two or more metrology devices and the at least one etch process sensor device.

Abstract: A wafer polish monitoring method and device for detecting the end point of the polishing of a conductive film with high precision and accuracy by monitoring the variation of the film thickness of the conductive film without adverse influence of slurry or the like after the film thickness of the conductive film decreases to an extremely small film thickness defined by the skin depth. A high-frequency transmission path is formed in a portion facing the conductive film on the surface of the wafer, the polishing removal state of the conductive film is evaluated based at least on the transmitted electromagnetic waves passing through the high-frequency transmission path or the reflected electromagnetic waves that are reflected without passing through the high-frequency transmission path, and the end point of the polishing removal and the point equivalent to the end point of the polishing removal are detected.

Abstract: A method of fabricating group-III nitride semiconductor laser device includes: preparing a substrate comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, where the laser structure includes a semiconductor region and the substrate, where the semiconductor region is formed on the semipolar principal surface; scribing a first surface of the substrate product in a direction of an a-axis of the hexagonal group-III nitride semiconductor to form first and second scribed grooves; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.

Abstract: An imager apparatus and methods are described. An embodiment of an imager module includes a plurality of groups of optical lenses, a lens frame, and at least one associated lens barrel configured to position and hold the plurality of groups of optical lenses. At least one of the groups of optical lenses is movable with respect to at least one other group of optical lenses for achieving optical focus. The imager module includes an integrated circuit (IC) imager die in proximity to the plurality of lenses, the imager die containing at least one image capture microelectronic device.

Abstract: A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.

Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.

Abstract: A method to manufacture an optical device with enhanced high frequency performance is disclosed. The method includes steps of: (a) forming semiconductor layers on a semiconductor substrate, (b) etching the semiconductor layers by using a mask to form a plurality of diffraction gratings, where the mask provides a plurality of periodic patterns each corresponding to respective gratings and having a specific pitch different from others, (c) forming an active layer on the etched semiconductor layers, (d) measuring a maximum optical gain of the active layer, (e) selecting one of diffraction gratings based on the measured optical gain, and (f) forming a current confinement structure aligned with the selected diffraction grating.

Abstract: Provided is a method of manufacturing a TFT substrate for preventing characteristics of a native oxide layer in a boundary between a microcrystal semiconductor layer and an amorphous semiconductor layer from being degraded. The method includes forming a gate electrode, forming a gate insulating film, modifying the formed first amorphous silicon thin film into a first crystalline silicon thin film, removing a silicon oxide layer on the surface of the first crystalline silicon thin film, forming the second amorphous silicon thin film, and dry etching the first crystalline silicon thin film and the second amorphous silicon thin film, and it is determined whether or not the in-process TFT substrate after the dry etching is returned to the processes after the dry etching by measuring the emission intensity of radicals in plasma during the dry etching and detecting the presence or absence of the silicon oxide layer in the boundary.

Abstract: At oxygen ion implanting steps in manufacture of a SIMOX wafer, a path is formed inside or on a back surface of wafer holding means, and oxygen ions are implanted while heating an outer peripheral portion of the wafer that is in contact with the wafer holding means by flowing a heated fluid through this path. An in-plane temperature of a wafer held at the time of ion implantation is prevented from becoming uneven, and in-plane film thicknesses of both an SOI layer and a BOX layer are uniformed.

Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate.

Abstract: Instead of monitoring the optical power coming out of a waveguide, a direct method of monitoring the optical power inside the waveguide without affecting device or system performance is provided. A waveguide comprises a p-i-n structure which induces a TPA-generated current and may be enhanced with reverse biasing the diode. The TPA current may be measured directly by probing metal contacts provided on the top surface of the waveguide, and may enable wafer-level testing. The p-i-n structures may be implemented at desired points throughout an integrated network, and thus allows probing of different devices for in-situ power monitor and failure analysis.

Abstract: Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam.

Abstract: A method for temperature control during a process of cleaving a plurality of free-standing thick films from a bulk material includes clamping a bulk material using a mechanical clamp device adapted to engage the bottom region of the bulk material through a seal with a planar surface of a stage to form a cavity with a height between the bottom region and the planar surface. The planar surface includes a plurality of gas passageways allowing a gas filled in the cavity with adjustable pressure. The method also includes maintaining the temperature of the surface region by processing at least input data and executing a control scheme utilizing at least one or more of; particle bombardment to heat the surface region; radiation to heat the surface region; and gas-assisted conduction between the bottom region and the stage.

Abstract: A substrate position detection method includes rotating the susceptor so that the substrate receiving portion is moved into an image taking area of a imaging apparatus; detecting first two position detection marks provided in the process chamber so that the first two position detection marks are within the image taking area, wherein a first perpendicular bisector of the first two position detection marks passes through a rotational center of the susceptor; detecting second two position detection marks provided in the susceptor so that the second two position detection marks can be within the image taking area, wherein a second perpendicular bisector of the second two position detection marks passes through the rotational center of the susceptor and a center of the substrate receiving portion; and determining whether the substrate receiving portion is positioned in a predetermined range in accordance with the detected first two and second two position detection marks.

Abstract: Solid state lighting (SSL) devices with good color uniformity and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a support structure, an SSL die in the support structure, and a converter material at least partially encapsulating the SSL die. The converter material is configured to emit under excitation. The converter material has a surface facing away from the SSL die, and the surface of the converter material has a generally convex shape.

Abstract: A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an inner-metal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.

Abstract: A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the gas pressure in the spaces, localized temperature of the component body can be precisely controlled. One or more heating elements can be arranged in each zone and a heat transfer liquid can be passed through the tubes to effect heating or cooling of each zone by activating the heating elements and/or varying pressure of the gas in the spaces.

Abstract: In a diffractive element, its grating pattern is so configured that a diffraction angle of a diffracted light beam of a light source that is subject to the first-order diffraction in a diffraction area is matched with an angle of a light beam passing through the diffractive area emitted from a light source and a light source position is matched with a light originating point of the light source that emits a light beam to be transmitted, and the center of light intensity distribution is matched with that of the light source passing through the diffractive element by inclining an optical axis of the light source. A position of the diffractive element is adjusted based on an electric current value generated when a reflected return path light beam of the light source is diffracted by the diffractive element and enters the light source.

Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.

Abstract: A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.

Abstract: A method of forming an electromechanical transducer device comprises forming on a fixed structure a movable structure and an actuating structure of the electromechanical transducer device, wherein the movable structure is arranged in operation of the electromechanical transducer device to be movable in relation to the fixed structure in response to actuation of the actuating structure. The method further comprises providing a stress trimming layer on at least part of the movable structure, after providing the stress trimming layer, releasing the movable structure from the fixed structure to provide a released electromechanical transducer device, and after releasing the movable structure changing stress in the stress trimming layer of the released electromechanical transducer device such that the movable structure is deflected a predetermined amount relative to the fixed structure when the electromechanical transducer device is in an off state.

Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.

Abstract: A method of manufacturing integrated circuits includes measuring a reflectivity value of a wafer. An optimum energy level for laser marking the wafer is determined using the reflectivity value. A laser beam having the optimum energy level is then emitted to make laser marks on the wafer.

Abstract: An aspect of the present invention relates to a method of analyzing an iron concentration of a boron-doped p-type silicon wafer by a SPV method, which comprises subjecting the wafer to Fe—B pair separation processing by irradiation with light and determining the iron concentration based on a change in a minority carrier diffusion length following the separation processing. The iron concentration is calculated with a calculation equation comprising a minority carrier diffusion length LAF1 measured after the separation processing, a minority carrier diffusion length LAF2 measured after a prescribed time has elapsed following measurement of LAF1, and dependence on time of recombination of Fe—B pairs separated by the separation processing. The calculation equation is derived by assuming that the irradiation with light causes boron atoms and oxygen atoms in the wafer to form a bonded product, and by assuming that the bonded product has identical influences on LAF1 and LAF2.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: A manufacturing yield of a semiconductor device (capacitive micromachined ultrasonic transducer) is increased. A plurality of first chips 1 in which a plurality of cells each having functions of transmitting and receiving ultrasonic waves are formed on a front surface of a first semiconductor wafer are manufactured, and each of the first chips 1 is judged as a superior/inferior product, and then, the first semiconductor wafer is sigulated into a plurality of first chips 1. Next, a plurality of second chips 2 in which a wiring layer is formed on a front surface of a second semiconductor wafer are manufactured, and each of the second chips 2 is judged as a superior/inferior product, and then, the second semiconductor wafer is sigulated into a plurality of second chips 2.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an array of bonding interconnects configured to provide electrical communication between the chip and a printed circuit board and reinforcement interconnects arranged around an outermost row of the array of bonding interconnects.

Abstract: An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material having an asperities-formed surface, and a pressure-sensitive adhesive layer laminated on the base material, and a film for semiconductor back surface laminated on the pressure-sensitive adhesive layer of the dicing tape, in which the dicing tape has a haze of at most 45%.

Abstract: When forming metal lines and vias in complex metallization systems of semiconductor devices, an additional control mechanism for adjusting the final critical dimension may be implemented in the last etch process for etching through the etch stop layer after having patterned the low-k dielectric material. To this end, the concentration of a polymerizing gas may be controlled in accordance with the initial critical dimension obtained after the lithography process, thereby efficiently re-adjusting the final critical dimension so as to be close to the desired target value.

Abstract: According to one embodiment, a pattern forming method comprises transferring a pattern formed in a surface of a template to a plurality of chip areas in a semiconductor substrate under different transfer conditions. Furthermore, the transferring the pattern formed in the surface of the template to the plurality of chip areas in the semiconductor substrate under the different transfer conditions comprises transferring the pattern formed in the surface of the template to the semiconductor substrate at least twice under each identical transfer condition. Moreover, the pattern forming method comprises dividing each of the plurality of chip areas into a plurality of areas, determining an optimum condition for each set of corresponding divided areas in the plurality of chip areas, and transferring the pattern onto the semiconductor substrate using the optimum transfer condition determined for each divided area.

Abstract: The present invention relates to a method for inspecting a light-emitting device, the method including performing a light emission test of (A) a light-emitting device including a lead frame having mounted and packaged thereon a plurality of light-emitting elements or (B) a light-emitting device obtained by resin encapsulating and packaging the light-emitting device (A), by applying a current to the plurality of light-emitting elements and judging each light-emitting element as passed or failed, in which arrangement of the plurality of light-emitting elements in the light-emitting device is set as in the following (?): (?) In a lead frame having a lattice form including a plurality of rows and a plurality of columns with a plurality of intersection points formed thereby, a plurality of light-emitting elements are disposed between the adjacent intersection points in each row, the adjacent light-emitting elements in each row are connected to each other so that positive electrode terminals or negative electrode t

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided.

Abstract: A solid-state imaging device according to one embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes a first input terminal electrode group that includes a plurality of terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and a first output terminal electrode that provides output signals. The solid-state imaging device further includes a second input terminal electrode group that includes a plurality of terminal electrodes for receiving the reset signal, the hold signal, the horizontal start signal, and the horizontal clock signal, a plurality of switches that switch an electrode group which is connected with integrating circuits, holding circuits, and a horizontal shift register between the first input terminal electrode group and the second input terminal electrode group, and a second output terminal electrode.

Abstract: A component for a light-emitting device includes a fluorescent layer that is capable of emitting fluorescent light and a housing that is connected to the fluorescent layer for housing a light-emitting diode.