Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.

Abstract: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000? to 1400? and the nitride is subsequently removed and a thin oxide, for example 320? is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract: A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

Abstract: A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.

Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area.

Abstract: A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by using wet etching and subsequently oxidizing a surface of the substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the substrate on the surface of the substrate; forming a second insulating film containing aluminum and another metal element on the first insulating film; forming a high-k insulating film containing at least one of hafnium and zirconium on the second insulating film; forming a metal film on the high-k insulating film; and conducting heat treatment to react the first insulating film and the second insulating film, thereby forming a third insulating film made of a mixture containing aluminum, the another metal element, the constituent element of the substrate, and oxygen.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

Abstract: A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.

Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.

Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.

Abstract: A method for tuning the work function of a metal gate of the PMOS device is disclosed. The method comprises depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO2 by high-temperature annealing so that the doped metal ions accumulate at the interface or generate dipoles by interfacial reaction, which in turn tunes the work function of the metal gate. The method can be widely used and its process is simple and convenient, has a better ability of tuning the work function of the metal gate, and is compatible with the conventional CMOS process.

Abstract: A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Abstract: In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.

Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

Abstract: A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0?x?1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0?y?1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

Abstract: A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.

Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.

Abstract: A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

Abstract: A semiconductor device includes: a semiconductor substrate; an interface layer formed on the semiconductor substrate; a high-k gate dielectric film formed on the interface layer; and a gate electrode formed on the high-k gate dielectric film. The high-k gate dielectric film contains La. The high-k gate dielectric film has the higher La concentration in an interface with the gate electrode than in an interface with the interface layer.

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract: A semiconductor device includes a first gate insulating film over a first device region, a second gate insulating film over a second device region, a first gate electrode over the first gate insulating film, a second gate electrode over the second gate insulating film, first source and drain regions in the first device region at both sides of the first gate electrode, second source and drain regions in the second device region at both sides of the second gate electrode, and a memory cell memory cell that further includes a tunnel insulating film formed over a third device region, a floating gate formed over the tunnel insulating film, an insulating film formed over the floating gate, a control gate formed over the tunnel insulating film, and third source and drain regions formed in third device region at both sides of the floating gate and the control gate.

Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.

Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer over the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at bast one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.

Abstract: A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate.

Abstract: A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region.

Abstract: At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers.

Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.

Abstract: In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a gate electrode on a substrate via a gate dielectric film; forming a first insulating film on the gate electrode, the first insulating film having a first groove in a central region of the first insulating film; and forming a halo region in the substrate below a side surface of the gate electrode, by injecting an impurity into the substrate through the first insulating film.

Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M?Oy) or amorphous metal oxynitride (M?OyNz).

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.

Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is disclosed as follows. A first oxide film in a first region and a second oxide film in a second region are formed on a semiconductor substrate. A high-k insulating film is formed on the first oxide film and the second oxide film. A film containing at least one of elements of Mg, La, Y, Dy, Sc, Al is formed on the high-k insulating film. After forming the film containing the element, thermal treatment is performed, so that the element in the film is diffused into the first oxide film and the second oxide film via the high-k insulating film. A metal gate electrode containing a metal material is formed on the high-k insulating film on the first oxide film and on the high-k insulating film on the second oxide film.

Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.

Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.

Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region