With Particular Manufacturing Method Of Gate Insulating Layer, E.g., Different Gate Insulating Layer Thicknesses, Particular Gate Insulator Materials Or Particular Gate Insulator Implants (epo) Patents (Class 257/E21.625)
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Publication number: 20110312171Abstract: Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.Type: ApplicationFiled: June 22, 2010Publication date: December 22, 2011Inventors: Chan Lim, Jennifer Lequn Liu, Brian Dolan, Saurabh Keshav, Hongbin Zhu
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Patent number: 8071447Abstract: A semiconductor device manufacturing method includes removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the substrate on the surface of the substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into an insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the substrate, and oxygen.Type: GrantFiled: February 11, 2010Date of Patent: December 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Tomonori Aoyama
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Patent number: 8043916Abstract: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.Type: GrantFiled: August 5, 2010Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Chan-Sik Park
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Patent number: 8044487Abstract: A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.Type: GrantFiled: December 15, 2006Date of Patent: October 25, 2011Assignee: Mitsubishi Electric CorporationInventors: Satoshi Rittaku, Kazuhiro Shimizu
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Patent number: 8022439Abstract: Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film.Type: GrantFiled: December 11, 2009Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 8012822Abstract: A process for forming dielectric films containing at least metal atoms, silicon atoms, and oxygen atoms on a silicon substrate comprises a first step of oxidizing a surface portion of the silicon substrate to form a silicon dioxide film; a second step of forming a metal film on the silicon dioxide film in a non-oxidizing atmosphere; a third step of heating in a non-oxidizing atmosphere to diffuse the metal atoms constituting the metal film into the silicon dioxide film; and a fourth step of oxidizing the silicon dioxide film containing the diffused metal atoms to form the film containing the metal atoms, silicon atoms, and oxygen atoms.Type: GrantFiled: December 23, 2008Date of Patent: September 6, 2011Assignees: Canon Kabushiki Kaisha, Canon Anelva CorporationInventors: Naomu Kitano, Yusuke Fukuchi, Nobumasa Suzuki, Hideo Kitagawa
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Patent number: 8008146Abstract: A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.Type: GrantFiled: December 4, 2009Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Andres Bryant, Guy Cohen, Jeffrey W. Sleight
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Patent number: 7994008Abstract: A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.Type: GrantFiled: January 26, 2007Date of Patent: August 9, 2011Assignee: STMicroelectronics (Crolles 2) SASInventors: Romain Wacquez, Philippe Coronel, Damien Lenoble, Robin Cerutti, Thomas Skotnicki
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Publication number: 20110189831Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.Type: ApplicationFiled: October 29, 2010Publication date: August 4, 2011Inventors: Stephan Kronholz, Berthold Reimer, Richard Carter, Fernando Koch, Gisela Schammler
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Patent number: 7989283Abstract: A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching.Type: GrantFiled: October 1, 2010Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventors: Shinichi Yamanari, Ryoichi Yoshifuku, Masaaki Shinohara, Takahiro Maruyama, Kenji Kawai, Yusaku Hirota
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Patent number: 7989903Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.Type: GrantFiled: April 9, 2010Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Kyoichi Suguro, Kouji Matsuo
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Patent number: 7989896Abstract: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the alType: GrantFiled: November 4, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Seiji Inumiya, Kazuaki Nakajima, Takashi Shimizu
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Patent number: 7989897Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: GrantFiled: November 26, 2008Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventor: Noriaki Maeda
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Patent number: 7989902Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.Type: GrantFiled: June 18, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Takashi Ando, Changhwan Choi, Martin M. Frank, Vijay Narayanan
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Patent number: 7989242Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.Type: GrantFiled: December 19, 2008Date of Patent: August 2, 2011Assignee: LG Display Co., Ltd.Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
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Patent number: 7972977Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.Type: GrantFiled: October 5, 2007Date of Patent: July 5, 2011Assignee: ASM America, Inc.Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
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Publication number: 20110156165Abstract: A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged on a protective film in the pixel region, a second common electrode overlapping the data line, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film and the organic insulation film, and has inclined surfaces connected to the protective film within the pixel region.Type: ApplicationFiled: December 10, 2010Publication date: June 30, 2011Inventors: Jin Hee JANG, Heung Lyul Cho
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Publication number: 20110159653Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: ApplicationFiled: March 10, 2011Publication date: June 30, 2011Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20110136312Abstract: The disclosure pertains to a semiconductor device and its manufacture method, the semiconductor device including non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. A semiconductor device and its manufacture method are to be provided, the semiconductor device having memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate (1) having first and second areas (AR1, AR2), a floating gate structure (4, 5, 6, 7, 8) for a non-volatile memory cell, a control gate structure (14) formed coupled to the floating gate structure, formed in the first area, and an insulated gate electrode (12, 14) for a logical circuit formed in the second area, wherein the floating gate structure has bird's beaks larger than those of the insulated gate electrode.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroshi Hashimoto, Kazuhiko Takada
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Patent number: 7951678Abstract: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V.Type: GrantFiled: August 12, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7943446Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating filmsType: GrantFiled: January 12, 2007Date of Patent: May 17, 2011Assignee: Sony CorporationInventor: Yuko Ohgishi
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Patent number: 7944004Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.Type: GrantFiled: March 26, 2009Date of Patent: May 17, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Mariko Takayanagi
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Patent number: 7943479Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.Type: GrantFiled: August 19, 2008Date of Patent: May 17, 2011Assignee: Texas Instruments IncorporatedInventors: Angelo Pinto, Manuel A. Quevedo-Lopez
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Patent number: 7939442Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.Type: GrantFiled: April 10, 2009Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Vassil Antonov, John Smythe
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Patent number: 7932153Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.Type: GrantFiled: October 26, 2009Date of Patent: April 26, 2011Assignee: Panasonic CorporationInventors: Takashi Nakabayashi, Hideyuki Arai, Mitsuo Nissa
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Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture
Publication number: 20110081758Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.Type: ApplicationFiled: October 13, 2010Publication date: April 7, 2011Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Pi-Tsung Chen, Ying-Tsung Chen -
Publication number: 20110076820Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: ApplicationFiled: September 30, 2010Publication date: March 31, 2011Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20110068412Abstract: By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.Type: ApplicationFiled: September 22, 2010Publication date: March 24, 2011Inventor: Yuichiro Kitajima
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Patent number: 7910429Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.Type: GrantFiled: April 7, 2004Date of Patent: March 22, 2011Assignee: ProMOS Technologies, Inc.Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Wai Leung, Chia-Shun Hsiao, George Kovall, Steven Ming Yang
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Patent number: 7910421Abstract: Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.Type: GrantFiled: May 30, 2008Date of Patent: March 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-jin Hyun, Si-young Choi, In-sang Jeom, Gab-jin Nam, Sang-bom Kang, Sug-hun Hong
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Patent number: 7902018Abstract: Embodiments of the present invention generally provide a method for forming a dielectric material with reduced bonding defects on a substrate. In one embodiment, the method comprises forming a dielectric layer having a desired thickness on a surface of a substrate, exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated dielectric layer on the substrate without etching the dielectric layer, and forming a gate electrode on the substrate. In certain embodiments, the fluorine source gas is a carbon free gas. In certain embodiments, the method further comprises co-flowing a gas selected from the group consisting of argon, helium, N2, O2, and combinations thereof with the fluorine source gas.Type: GrantFiled: September 26, 2007Date of Patent: March 8, 2011Assignee: Applied Materials, Inc.Inventors: Philip Allan Kraus, Christopher Olsen, Khaled Z. Ahmed
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Patent number: 7897456Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.Type: GrantFiled: June 26, 2009Date of Patent: March 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Nam-Jae Lee
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Patent number: 7898015Abstract: An insulating film includes a first metal, oxygen, fluorine and one of a second metal or nitrogen, and satisfies {k×[X]?[F]}/2?8.4 atomic %, wherein the fluorine amount [F], the one element amount [X], and a valence number difference k between the first and second metals or between oxygen and nitrogen.Type: GrantFiled: March 21, 2007Date of Patent: March 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Masato Koyama
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Patent number: 7893508Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.Type: GrantFiled: September 11, 2006Date of Patent: February 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tsunehisa Sakoda, Kazuto Ikeda
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Patent number: 7893439Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.Type: GrantFiled: January 4, 2008Date of Patent: February 22, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Shunpei Yamazaki, Kengo Akimoto
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Patent number: 7892959Abstract: A method of manufacturing a flash memory device that may include forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate; sequentially forming a dielectric film pattern and a second polysilicon pattern on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern; forming a second oxide film pattern on the second polysilicon pattern; forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, the dielectric film pattern and the second polysilicon pattern; removing the second oxide film pattern; forming a spacer on sidewalls of the gate; and forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer.Type: GrantFiled: June 25, 2008Date of Patent: February 22, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sung-Jin Kim
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Patent number: 7892913Abstract: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.Type: GrantFiled: March 13, 2009Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Nakajima
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Patent number: 7883974Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.Type: GrantFiled: September 17, 2009Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Kobayashi, Katsuyuki Sekine, Tomonori Aoyama, Hiroshi Tomita
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Patent number: 7883967Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.Type: GrantFiled: July 24, 2006Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
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Patent number: 7879688Abstract: A method of making an electronic device comprises solution depositing a dielectric composition onto a substrate and polymerizing the dielectric composition to form a gate dielectric. The dielectric composition comprises a polymerizable resin and zirconium oxide nanoparticles.Type: GrantFiled: June 29, 2007Date of Patent: February 1, 2011Assignee: 3M Innovative Properties CompanyInventors: James C. Novack, Dennis E. Vogel, Brian K. Nelson
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Patent number: 7875938Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.Type: GrantFiled: December 1, 2008Date of Patent: January 25, 2011Assignee: Macronix International Co., Ltd.Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu
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Patent number: 7871942Abstract: Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.Type: GrantFiled: March 27, 2008Date of Patent: January 18, 2011Assignee: Applied Materials, Inc.Inventors: Shreyas S. Kher, Pravin K. Narwankar, Khaled Z. Ahmed, Yi Ma
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Publication number: 20110006375Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.Type: ApplicationFiled: September 21, 2010Publication date: January 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 7863127Abstract: After forming a first gate electrode and a second gate electrode on a semiconductor substrate, a silicon oxide film is formed to cover an n-channel MISFET forming region, and a p-channel MISFET forming region is exposed. Subsequently, after a first element supply film made of, for example, an aluminum oxide film is formed on the whole surface of the semiconductor substrate, a heat treatment is performed. By this means, a high-concentration HfAlO film and a low-concentration HfAlO film are formed by diffusing aluminum into the first insulating film just below the second gate electrode. Thereafter, by using a magnesium oxide film as a second element supply film, magnesium is diffused into the first insulating film just below the first gate electrode, thereby forming a high-concentration HfMgO film and a low-concentration HfMgO film.Type: GrantFiled: May 22, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Nobuyuki Mise, Tetsu Morooka
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Patent number: 7863694Abstract: A thin film transistor having an improved gate dielectric layer is disclosed. The gate dielectric layer comprises a poly(hydroxyalkyl acrylate-co-acrylonitrile) based polymer. The resulting gate dielectric layer has a high dielectric constant and can be crosslinked. Higher gate dielectric layer thicknesses can be used to prevent current leakage while still having a large capacitance for low operating voltages. Methods for producing such gate dielectric layers and/or thin film transistors comprising the same are also disclosed.Type: GrantFiled: October 14, 2008Date of Patent: January 4, 2011Assignee: Xerox CorporationInventors: Ping Liu, Yiliang Wu, Yuning Li, Paul F. Smith
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Publication number: 20100327368Abstract: High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy.Type: ApplicationFiled: June 28, 2010Publication date: December 30, 2010Inventors: Stephan KRONHOLZ, Carsten REICHEL, Falk GRAETSCHE, Boris BAYHA
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Patent number: 7858536Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.Type: GrantFiled: September 20, 2007Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
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Publication number: 20100320504Abstract: Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film.Type: ApplicationFiled: December 11, 2009Publication date: December 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KAJIYAMA
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Patent number: 7851788Abstract: To provide an organic transistor which can achieve a reduced leak current from a gate electrode. An organic transistor including a substrate 1, a pair of a source electrode 4 and a drain electrode 5, an organic semiconductor layer 6 provided between the source electrode 4 and the drain electrode 5, and a gate electrode 2 provided in association with the organic semiconductor 6 with a gate insulating layer 3 interposed therebetween, wherein the gate insulating layer 3 has a stacked structure including at least an organic insulating layer 3a and an inorganic barrier layer 3b.Type: GrantFiled: December 27, 2006Date of Patent: December 14, 2010Assignee: Pioneer CorporationInventor: Satoru Ohta
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Publication number: 20100308410Abstract: System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area.Type: ApplicationFiled: June 9, 2009Publication date: December 9, 2010Inventors: Martin Ostermayr, Chandraserhar Sarma