Interconnection Or Wiring Or Contact Manufacturing Related Aspects (epo) Patents (Class 257/E21.627)
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Patent number: 11864376Abstract: A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.Type: GrantFiled: July 8, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shan Wang, Shun-Yi Lee
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Patent number: 11832438Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
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Patent number: 11637018Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.Type: GrantFiled: October 27, 2020Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
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Patent number: 11616054Abstract: A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.Type: GrantFiled: May 8, 2020Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou Sio, Sang-Chi Huang
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Patent number: 11616150Abstract: A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.Type: GrantFiled: January 20, 2021Date of Patent: March 28, 2023Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventor: Huilong Zhu
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Patent number: 11532561Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.Type: GrantFiled: August 4, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
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Patent number: 11521967Abstract: A substrate has an active area including first and second doped regions separated by portions of the substrate. Gates are located over the active area, each gate formed extending over a portion of the substrate separating adjacent first and second doped regions. A length of the doped regions is greater than other devices within the substrate that have a same gate oxide thickness. A first metallization layer has first electrical connectors between each of the first doped regions and a gate immediately adjacent thereto, and second electrical connectors connected to each of the second doped regions. A second metallization layer has a first electrical connector connected to each first electrical connector of the first metallization layer, and a second electrical connector connected to each second electrical connector of the first metallization layer, with the second electrical connector of the second metallization layer not overlapping the gates.Type: GrantFiled: June 23, 2020Date of Patent: December 6, 2022Assignee: STMicroelectronics International N.V.Inventor: Vishal Kumar Sharma
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Patent number: 11488929Abstract: A bonding apparatus configured to bond substrates comprises a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder, and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a mover configured to move the first holder and the second holder relatively in a horizontal direction; a laser interferometer system configured to measure a position of the first holder or the second holder which is moved by the mover; a linear scale configured to measure a position of the mover; and a controller configured to control the mover based on a measurement result of the laser interferometer system and a measurement result of the liner scale.Type: GrantFiled: October 11, 2017Date of Patent: November 1, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Takashi Nakamitsu, Shuhei Matsumoto, Yosuke Omori
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Patent number: 9041216Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: June 19, 2013Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Patent number: 9006834Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.Type: GrantFiled: March 18, 2014Date of Patent: April 14, 2015Assignee: Advanced Micro Devices, Inc.Inventor: Richard T Schultz
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Patent number: 8936989Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.Type: GrantFiled: April 10, 2008Date of Patent: January 20, 2015Inventor: Tzu-Yin Chiu
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Patent number: 8907463Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.Type: GrantFiled: April 26, 2011Date of Patent: December 9, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Kayoko Shibata, Hiroaki Ikeda
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Patent number: 8895392Abstract: A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate.Type: GrantFiled: December 19, 2012Date of Patent: November 25, 2014Assignee: SK Hynix Inc.Inventors: Tae-Yoon Kim, Heung-Jae Cho
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Patent number: 8896136Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.Type: GrantFiled: June 30, 2010Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8865588Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.Type: GrantFiled: December 24, 2013Date of Patent: October 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takeshi Kagawa
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Patent number: 8778757Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.Type: GrantFiled: July 3, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Sang-sup Jeong
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Patent number: 8741751Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.Type: GrantFiled: August 10, 2012Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
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Patent number: 8709862Abstract: Al pastes with additives of Co, Sr, V, compounds thereof and combinations thereof improve both the physical integrity of a back contact of a silicon solar cell as well as the electrical performance of a cell with such a contact.Type: GrantFiled: January 3, 2012Date of Patent: April 29, 2014Assignee: Heraeus Precious Metals North America Conshohocken LLCInventors: Hong Jiang, Chandrashekhar S. Khadilkar, Nazarali Merchant, Srinivasan Sridharan, Aziz S. Shaikh
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Patent number: 8697535Abstract: A thin film transistor substrate includes a substrate, a gate electrode on the substrate, an active layer on or below the gate electrode (the active layer at least partially overlapping the gate electrode) including a first active region and a second active region, the first active region and the second active region facing each other and extending beyond the gate electrode, a source electrode electrically connected to the first active region and a drain electrode electrically connected to the second active region, wherein the active layer includes a recess region which is at least partially recessed from a surface of the active layer facing the gate electrode, and the recess region includes a portion extending between the first active region and the second active region.Type: GrantFiled: December 16, 2011Date of Patent: April 15, 2014Assignee: Samsung Display Co., Ltd.Inventors: Tae-Jin Kim, Sang-Jae Yeo, Dae-Sung Choi
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Patent number: 8659173Abstract: An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.Type: GrantFiled: January 4, 2013Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee
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Patent number: 8658524Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.Type: GrantFiled: December 2, 2010Date of Patent: February 25, 2014Assignee: Cambridge Silicon Radio LimitedInventors: Rainer Herberholz, David Vigar
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Patent number: 8642464Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.Type: GrantFiled: July 31, 2012Date of Patent: February 4, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takeshi Kagawa
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Patent number: 8624370Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit.Type: GrantFiled: March 20, 2009Date of Patent: January 7, 2014Assignee: Stats Chippac Ltd.Inventors: HeeJo Chi, NamJu Cho, Taewoo Lee
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Patent number: 8614509Abstract: A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.Type: GrantFiled: September 27, 2012Date of Patent: December 24, 2013Assignee: SK Hynix Inc.Inventor: Jung Nam Kim
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Patent number: 8569168Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.Type: GrantFiled: February 13, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 8569163Abstract: A risk of an electrical short between electrode pads of a semiconductor device can be reduced to thereby improve quality of the semiconductor device. During ball bonding in wire bonding, in each of the electrode pads of a semiconductor chip which are arrayed along an ultrasonic wave application direction (ultrasonic vibration direction), a ball at the tip of a copper wire and the electrode pad are coupled to each other while being rubbed against each other in a direction intersecting the ultrasonic wave application direction. Thus, the amount of AL splash formed on the electrode pad can be minimized to make the AL splash smaller. As a result, the quality of the semiconductor device assembled by the above-mentioned ball bonding can be improved.Type: GrantFiled: December 22, 2011Date of Patent: October 29, 2013Assignee: Renesas Electronics CorporationInventors: Masahiko Sekihara, Takanori Okita
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Patent number: 8564068Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.Type: GrantFiled: January 5, 2012Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ya Hui Chang
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Patent number: 8525247Abstract: A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.Type: GrantFiled: May 3, 2012Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Jin Park, Hyun-Su Ju, In-Gyu Baek
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Patent number: 8507375Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.Type: GrantFiled: February 2, 2012Date of Patent: August 13, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: André P. Labonté, Richard S. Wise
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Patent number: 8502383Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.Type: GrantFiled: September 23, 2011Date of Patent: August 6, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Christian Rivero
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Publication number: 20130175637Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Ya Hui Chang
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Patent number: 8456883Abstract: CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.Type: GrantFiled: May 29, 2012Date of Patent: June 4, 2013Assignee: Headway Technologies, Inc.Inventor: Daniel Liu
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Patent number: 8436469Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.Type: GrantFiled: June 7, 2012Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
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Patent number: 8435876Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.Type: GrantFiled: November 2, 2011Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jongchul Park, Jong-Kyu Kim, Ki-jin Park, Sangsup Jeong
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Patent number: 8431968Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.Type: GrantFiled: July 28, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You
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Patent number: 8404587Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.Type: GrantFiled: June 14, 2011Date of Patent: March 26, 2013Assignee: Micro Technology, Inc.Inventors: Kyle K. Kirby, Kunal R. Parekh
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Patent number: 8405219Abstract: A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.Type: GrantFiled: June 7, 2012Date of Patent: March 26, 2013Assignee: Renesas Electronics CorporationInventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
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Patent number: 8404585Abstract: An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.Type: GrantFiled: July 7, 2011Date of Patent: March 26, 2013Assignee: Research Triangle InstituteInventor: Robert O. Conn
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Patent number: 8394697Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.Type: GrantFiled: January 20, 2011Date of Patent: March 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
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Patent number: 8390098Abstract: A semiconductor device 100 is provided with a multiplex through plug 111 that fills an opening extending through the silicon substrate 101. The multiplex through plugs 111 comprises a column-shaped and solid first through electrode 103, a first insulating film 105 that covers the cylindrical face of the first through electrode 103, a second through electrode 107 that covers the cylindrical face of the first insulating film 105 and a second insulating film 109 that covers the cylindrical face of the second through electrode 107, and these have a common central axis. The upper cross sections of the first insulating film 105, the second through electrode 107 and the second insulating film 109 are annular-shaped.Type: GrantFiled: May 6, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventor: Satoshi Matsui
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Patent number: 8372718Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.Type: GrantFiled: September 10, 2012Date of Patent: February 12, 2013Assignee: Renesas Electronics CorporationInventors: Yasuhiro Fujii, Kazumasa Yonekura, Tatsunori Kaneoka
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Patent number: 8373177Abstract: An LED light source can include protection members to protect bonding wires. The LED can include a substrate including electrode patterns, a sub mount substrate located on the substrate, at least one flip LED chip mounted on the sub mount substrate and a phosphor rein covering the LED chip. The bonding wires can connect each of the electrode patterns to conductor patterns connecting to electrodes of the LED chip. The protection members can be located so as to surround both sides of the bonding wires. In addition, because each height of the protection members is higher than each maximum height of the bonding wires and is lower than a height of the phosphor resin, the protection members can protect the bonding wires from external pressure while the light flux is not reduced. Thus, the disclosed subject matter can provide a reliable LED light source having a favorable light distribution.Type: GrantFiled: October 12, 2010Date of Patent: February 12, 2013Assignee: Stanley Electric Co., Ltd.Inventors: Hiroshi Kotani, Takahiko Nozaki
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Patent number: 8373262Abstract: A source driver of a film package type including a film substrate; a semiconductor chip on a surface of the film substrate, the semiconductor chip having a plurality of terminals, the plurality of terminals including input terminals, output terminals, and third terminals; an input terminal wiring region for receiving first wiring lines which are connected to the input terminals; an output terminal wiring region for receiving second wiring lines which are connected to the output terminals; sprocket portions at opposite ends of the film substrate; and a heat conducting patterns for connecting the third terminals. This makes it possible to provide a source driver, a method for manufacturing the source driver, and a liquid crystal module, each of which can increase a heat dissipation amount.Type: GrantFiled: November 27, 2008Date of Patent: February 12, 2013Assignee: Sharp Kabushiki KaishaInventor: Tatsuya Katoh
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Patent number: 8334596Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and further including copper (Cu), a coupling ball primarily including Cu, the coupling ball is coupled to the electrode pad such that a plurality of layers of Cu and Al alloys are formed at a junction between the electrode pad and the coupling ball, and an encapsulating resin including a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and the junction between the electrode pad and the coupling ball. A dimensional area of the plurality of layers of Cu and Al alloys is equal to or larger than 50% of a dimensional area of the junction between the electrode pad and the coupling ball. The plurality of layers of Cu and Al alloys includes a CuAl2 layer, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.Type: GrantFiled: April 4, 2011Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Takekazu Tanaka, Kouhei Takahashi, Seiji Okabe
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Patent number: 8319264Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.Type: GrantFiled: December 28, 2010Date of Patent: November 27, 2012Assignee: SK Hynix Inc.Inventor: Seung Bum Kim
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Patent number: 8304908Abstract: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.Type: GrantFiled: March 19, 2009Date of Patent: November 6, 2012Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku UniversityInventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
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Patent number: 8288232Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.Type: GrantFiled: January 13, 2010Date of Patent: October 16, 2012Assignee: Renesas Electronics CorporationInventors: Yasuhiro Fujii, Kazumasa Yonekura, Tatsunori Kaneoka
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Patent number: 8258059Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.Type: GrantFiled: January 3, 2011Date of Patent: September 4, 2012Assignee: Oki Semiconductor Co., Ltd.Inventor: Tomohiro Yakuwa
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Publication number: 20120181623Abstract: It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.Type: ApplicationFiled: February 27, 2011Publication date: July 19, 2012Applicant: INSTITUTE OF MICRORLRCTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
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Patent number: 8217484Abstract: The image sensor includes a substrate; a wiring structure formed on a front side of the substrate and including a plurality of wiring layers and a plurality of insulating films; a first well formed within the substrate and having a first conductivity type; and a first metal wiring layer directly contacting a backside of the substrate and configured to apply a first well bias to the first well.Type: GrantFiled: March 26, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Byung Jun Park