Abstract: A thin film transistor array panel including a substrate, a plurality of first signal lines formed on the substrate, a plurality of second signal lines, insulated from the first signal lines, which are formed on the substrate and which define an area of a display area by traversing the first signal lines, a driver disposed on a peripheral area, a plurality of connection lines, disposed on the peripheral area, which couple the driver to each of the first signal lines, and an insulating layer which insulate the first signal lines from the connection lines. The insulating layer includes a plurality of contact holes, portions of the first signal lines and the connection lines are connected through the contact holes, and sizes of exposed portions of the first signal lines exposed through the contact holes increase as respective distances from the contact holes to the driver increase.

Abstract: A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Abstract: An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region.

Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.

Abstract: A liquid crystal display (LCD) includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; an active pattern formed as an island on the gate electrode and having a width smaller than the gate electrode; an insulation film formed on the first substrate and having first and second contact holes exposing source and drain regions of the active pattern, respectively; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the first and second contact holes; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region; an etch stopper positioned between the source and drain electrodes and formed as an insulation film; a pixel electrode electrically connected with the drain electrode; and a second substrate attached with the first substrate in a facing ma

Abstract: A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stopper film formed on the gate electrode and first element region to cover the first element region and giving a tensile stress, a second stopper film formed on the gate electrode and second element region to cover the second element region and giving a compressive stress, and a contact connected to the gate electrode on the element isolation insulating film. The first and second stopper films overlap each other at least partially on the element isolation insulating film, and a total thickness of the first and second stopper films on the gate electrode on the element isolation insulating film is smaller than a total thickness outside the gate electrode.

Abstract: An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer fills the vias and forms a metallization pad that is suitable for supporting a solder bump. Preferably the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad. Each metallization pad is electrically connected to the contact pad through a plurality of the vias. The described under bump structures can be formed at the wafer level.

Abstract: A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the insulating layer over the first conductive layer. Each of the first and second conductive layers is formed by discharging drops of a solvent containing fine particles of a conductive material. The insulating layer is formed by discharging drops of a solvent containing fine particles of an insulating material.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Abstract: Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole.

Abstract: A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts.

Abstract: A method for fabricating metal wirings of a semiconductor including forming an etch stop layer on a semiconductor substrate, and forming an inter metal dielectric on the etch stop layer. The method also includes forming a via hole in the inter metal dielectric so as to expose the etch stop layer, and forming a trench on the inter metal dielectric so as to expose the via hole. The method further includes removing the etch stop layer exposed through the via hole, wet etching an inner wall of the trench, and forming a metal wiring inside the via hole and the trench.

Abstract: A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.

Abstract: High quality dielectric layers may be achieved without introducing excessive impurities when a semiconductor device is manufactured by a method that includes forming a lower wire layer on a structure above a semiconductor substrate, forming a silicon rich oxide layer having a refractive index of 0.45-1.55 on the lower wire layer and the structure, implanting carbon and oxygen (e.g., CO2) into the silicon rich oxide (SRO) layer, and forming an organosilicate glass layer by heat-treating the implanted SRO layer.

Abstract: In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface and the silicon oxide and an opening is produced in the layer, the opening abutting on the silicon oxide. The selectively grown silicon oxide is removed and the opening is filled with electrically conductive material, whereby the electrically conductive material forms the contact.

Abstract: Resist films 19 for liftoff are formed on an insulating layer 12 corresponding to a wiring formation region A so as to expose the insulating layer 12 corresponding to formation positions of first seed layers 14 and thereafter, metal films 21 are formed. Then, the resist films 19 for liftoff are removed and the first and second seed layers 14, 22 are formed. Thereafter, conductive metals 15 are precipitated and grown on the first seed layers 14 by an electrolytic plating method and thereafter the second seed layers 22 are removed and thereby, wirings 13 made of the first seed layers 14 and the conductive metals 15 are formed.

Abstract: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, a second heat treatment is performed for releasing stress generated in the substrate in the first heat-treatment. Thereafter, an impurity is implanted into an area to become an implanted region of the substrate, using the gate electrodes as masks, and a third heat treatment is performed for activating the impurity implanted.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper layer insulating film is provided on the first semiconductor construct and insulating layer. Upper layer wiring lines are provided on the upper layer insulating film so that the upper layer wiring line is electrically connected to the external connection electrode. A second semiconductor construct is joined to and installed on connection pad portions. All jointing portions of the second semiconductor construct for the connection pad portions of the upper layer wiring lines are disposed in a region corresponding to the first semiconductor construct.

Abstract: A method of manufacturing semiconductor devices, including the steps of forming an interlayer insulating layer over a semiconductor substrate in which a predetermined structure including a drain is formed, etching a part of the interlayer insulating layer to form a contact hole, and then forming a first conductive film on the entire structure including the contact hole, blanket-etching the first conductive film so that the first conductive film remains on a surface of the contact hole, forming a second conductive film on the entire structure, burying a contact hole, and then performing a blanket-etch or CMP process using the interlayer insulating layer as a stopper, and forming a metal line layer on the entire structure.

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the copper layer.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of forming the wiring according to the present invention. According to the present invention, when a wiring material and the like is directly patterned on a substrate mainly having an insulating surface by droplet discharging method, a wiring is formed at a position including at least an opening in contact with an underlying portion on an insulating film provided with the opening by dropping a liquid droplet containing a conductive composition by droplet discharging method. By heating the substrate with the wiring formed thereon, a surface of the wiring on the opening and a surface of the wiring other than the wiring on the opening are approximately leveled, and the opening is filled.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.

Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Abstract: A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes.

Abstract: Wiring structures of semiconductor devices and fabrication methods thereof. A metal layer electrically connected to at least one vertical connection formed in an insulating layer is provided. A dummy dielectric layer is formed in a portion of the metal layer. The dummy dielectric layer is located in a region adjacent to the vertical connection.