Abstract: A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.

Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.

Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.

Abstract: The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device.

Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of Zrx Hfy Sn1-x-y O2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.

Abstract: Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.

Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.

Abstract: A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well.

Abstract: A first liner and a second liner are formed such that a peripheral portion of the second liner overlies a peripheral portion of the first liner. A photoresist layer is applied and patterned such that a sidewall of a patterned photoresist layer overlies an overlapping peripheral portion of the second liner An isotropic dry etch is performed to laterally etch the overlapping peripheral portion of the second liner from below the patterned photoresist layer. The patterned photoresist is subsequently removed, and a structure without an overlap of the first and second liners is provided.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.

Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.

Abstract: A time clock clearly identifies where a user should position a time card therein. The clock and a printer platen are fixed relative to a base, and has the time card rests thereon. A printing mechanism moves relative to the base and has a target area, it is traversable between a print position and an idle position, and it impresses the time indicia onto the time card while in the print position. A ribbon shield is fixed relative to the base. A focused illuminated guide is fixed relative to the base, and in combination with the ribbon shield, guides the time card with respect to the printing mechanism to clearly identify where the user should position the time card in the time clock.

Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.

Abstract: A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Abstract: A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

Abstract: In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.

Abstract: A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase.

Abstract: A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.

Abstract: A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film covering the second transistor device and exposing the first transistor device on the substrate; performing a pre-amorphous implantation (PAI) process to form an amorphous layer respectively at two sides of the first transistor device, and removing the patterned stress film.

Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.

Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

Abstract: A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract: A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

Abstract: A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 ? to 50 ? on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.

Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

Abstract: A semiconductor device includes a first fin formed of a first semiconductor material and a second fin comprising a layer formed of a second semiconductor material. The first semiconductor material is silicon, and the second semiconductor material is silicon-germanium (SiGe). The second fin further includes a layer of the first semiconductor material below the layer of the second semiconductor material. The semiconductor device also includes a hard mask layer on the first and second fins and an insulator layer that is disposed below the first and second fins. The first and second fins are used to form an N-channel and a P-channel semiconductor device, respectively.

Abstract: A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.

Abstract: An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

Abstract: A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.

Abstract: The present invention relates to a MOS device and method of manufacturing the same. The device comprises a semiconductor substrate; a channel formed in the semiconductor substrate; a gate stack formed on the channel and a spacer surrounding the gate stack; and source and drain regions formed in the substrates on both sides of the spacer; wherein the gate stack is comprised of an insulating layer and a multi-layer metal gate formed thereon, the multi-layer metal gate is comprised of a strained metal layer for introducing a stress to the channel and a work function regulating layer for regulating the work function of the metal gate, and the work function regulating layer surrounds the strained metal layer from the bottom and sides. The multi-layer metal gate structure overcomes the defect incurred by the fact that a conventional strained metal gate material can not achieve both regulation of work function and effect of application of strain be optimized at the same time.

Abstract: Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.