Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a metal interconnect, and a magnetic tunneling junction (MTJ). The transistor region includes a gate over the substrate, and a doped region is at least partially in the substrate. The metal interconnect is over the doped region. The metal interconnect includes a metal via. The MTJ is entirely underneath the metal interconnect and between the doped region and the metal via, and a diameter of a bottom surface of the MTJ is greater than a diameter of an upper surface of the MTJ.

Abstract: Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.

Abstract: A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.

Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.

Abstract: A magnetic memory device is provided. The magnetic memory device includes: (i) a cylindrical core, (ii) a metallic buffer layer that surrounds the cylindrical core, (iii) a first ferromagnetic layer that surrounds the metallic buffer layer, (iv) a barrier layer that surrounds the first ferromagnetic layer, and (v) a second ferromagnetic layer that surrounds the barrier layer. The cylindrical core, the metallic buffer layer, the first ferromagnetic layer, the barrier layer, and the second ferromagnetic layer collectively form a magnetic tunnel junction.

Abstract: A dual nitride landing pad for a high performance magnetoresistive random access memory (MRAM) device is formed on a recessed surface of the least one electrically conductive structure in a MRAM device area. The dual nitride landing pad includes a bottom metal nitride landing pad and a TaN-containing landing pad.

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract: This invention relates to structures comprising magnetic materials and conjugated molecules. The invention relates to magneto-resistive devices based on such structures. Structures and devices of the invention can be used as magnetic switches, magnetic sensors and in devices such in/as memory devices.

Abstract: Embodiments relate to magnetoresistive (xMR) sensors. In an embodiment, an xMR stack structure is configured to form two different xMR elements that can be coupled to form a locally differential Wheatstone bridge. The result is a highly sensitive magnetic sensor with small dimensions and robustness against thermal drift and sensor/encoder pitch mismatch that can be produced using standard processing equipment. Embodiments also relate to methods of forming and patterning the stack structure and sensors that provide information regarding direction in addition to speed.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.

Abstract: A spintronic device can include a bottom contact layer, a bottom magnetic layer disposed on the bottom contact layer, a nanoparticle layer disposed on the bottom magnetic layer, a top magnetic layer disposed on the nanoparticle layer, and a top contact layer disposed on the top magnetic layer. The spintronic device can include a bottom insulation layer disposed between the bottom magnetic layer and the nanoparticle layer, and a top insulation layer disposed between the nanoparticle layer and the top magnetic layer.

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A hard mask material is deposited over a magnetic memory element material, and a chemical template layer such as brush or mat material is deposited over the hard mask. A mask structure is formed over the soluble polymer. The mask structure is configured with openings having a center to center spacing that is an integer multiple of a block copolymer material. The openings in the mask structure can be shrunk by depositing a spacer material. The chemical template layer is chemically patterned, such as by a quick plasma exposure and the mask is removed. A block copolymer material is then deposited over the chemical template and annealed to form block copolymer cylinders that are located over the patterned portions of the chemical template and between the patterned portions.

Abstract: Semiconductor devices and semiconductor device control methods are described. A semiconductor device comprises a first electrode; a cell arranged on the first electrode and including a magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; and a heating element to form a thermal gradient in the first electrode.

Abstract: According to some aspects, a layered structure comprises a memory layer exhibiting magnetization perpendicular to a face of the memory layer, the memory layer configured to change a direction of the magnetization in response to application of a current thereto, a magnetic layer exhibiting magnetization parallel or antiparallel to the direction of the magnetization of the memory layer and comprising a plurality of ferromagnetic layers, one or more non-magnetic layers, and an antiferromagnetic material, wherein a first non-magnetic layer of the one or more non-magnetic layers is situated between a first ferromagnetic layer of the plurality of ferromagnetic layers and a second ferromagnetic layer of the plurality of ferromagnetic layers, and wherein the antiferromagnetic material contacts at least one of the first non-magnetic layer and the first ferromagnetic layer, and an intermediate layer formed from a non-magnetic material located between the memory layer and the magnetic layer.

Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.

Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more uniformity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.

Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.

Abstract: According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first ferromagnetic layer and a first nonmagnetic layer disposed on the first ferromagnetic layer; a magnetoresistive effect element including a second ferromagnetic layer disposed on the first nonmagnetic layer, a third ferromagnetic layer, and a second nonmagnetic layer disposed between the second and the third ferromagnetic layer; a first transistor having a first terminal connected to the first ferromagnetic layer, and a second terminal connected to a source line; and a second transistor having a first terminal connected to the third ferromagnetic layer, and a second terminal connected to a bit line.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.

Abstract: A magnetic domain wall (MDW) motion device. The MDW motion device may include a ferromagnetic layer with perpendicular magnetic anisotropy and non-magnetic metal layers extending parallel to and in contact with the ferromagnetic layer. The ferromagnetic layer may include first ferromagnetic regions, which are arranged in an extension direction of the ferromagnetic layer, and second ferromagnetic regions, which are provided between an adjacent pair of the first ferromagnetic regions. The first and second ferromagnetic regions may have spin torque coefficients of opposite signs, and an MDW positioned near an interface between the first and second ferromagnetic regions may be moved by an in-plane current flowing through the non-magnetic metal layer.

Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) layer over the bottom electrode, a top electrode over the MTJ layer, and a (N+1)th metal layer over the top electrode. The top electrode includes material having an oxidation rate lower than that of Tantalum or Tantalum derivatives. N is an integer greater than or equal to 1.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column.

Abstract: We describe the manufacturing process for and structure of a CPP MTJ MRAM unit cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The cell is formed of a vertically or horizontally series connected sequence of N sub-cells, each sub-cell being an identical MTJ element. A statistical population of such multiple sub-cell unit cells has a variation of resistance that is less by a factor of N?1/2 than that of a population of single sub-cells. As a result, such unit cells have an improved read margin while not requiring an increase in the critical switching current.

Abstract: Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.

Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes a reference layer, a free layer, a nonmagnetic spacer layer between the reference and free layers, and a rare earth-transition metal (RE-TM) layer in the reference and/or free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. If the RE-TM layer is in the free layer then the RE-TM layer is between hard and soft magnetic layers in the free layer. In this aspect, the RE-TM layer has a standby magnetic moment greater than a write magnetic moment. If the RE-TM layer is in the reference layer, then the magnetic junction includes a second RE-TM layer. In this aspect, a first saturation magnetization quantity of the RE-TM layer matches a second saturation magnetization quantity of the second RE-TM layer over an operating temperature range.

Abstract: A magnetic field sensor including a first plurality and a second plurality of magnetoresistive sensors, wherein each magnetoresistive sensor of the first plurality and the second plurality of magnetoresistive sensors comprises: an electrode; a reference layer adjacent to the electrode, wherein the reference layer includes a synthetic antiferromagnetic structure; a magnetic sense element; and an intermediate layer between the reference layer and the magnetic sense element; and one or more conductors configured to electrically couple the magnetoresistive sensors of the first plurality and the second plurality in various configurations.

Abstract: A resistive input system is disclosed, which includes a resistor matrix. The resistor matrix includes M first traces, N second traces, and M*N resistors. First ends of the resistors of a same column are coupled to one of the M first traces, second ends of the resistors of a same row are coupled to one of the N second traces, M is integers greater than 1, and N is integers greater than and equal to 1. The M*N resistors include variable resistors. A measurement circuit measures variations of a first voltage level of each of the second traces while a power control circuit provides the first voltage to the one of the M first traces and the second voltage to the rest of the M first traces. At least one input point is determined according to the variation of the first voltage level of each of the second traces.

Abstract: Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional (2D) topological insulator (TI) having an active area body. One or a pair of ferromagnetic storage units are provided on top of the 2D TI with a dielectric and a gate thereon. A first contact can be at one end of the 2D TI and a second contact can be at the other end of the 2D TI, with the one or pair of ferromagnetic storage units on the 2D TI between the two contacts to facilitate 2D TI transport along a one-dimensional edge of the first and/or second lateral side. Application of biases via the gate and the first and second contacts enable read and write operations.

Abstract: According to embodiments of the present invention, a sensor array for reading data from a storage medium including a plurality of tracks is provided. The sensor array includes a first sensor, and a second sensor, wherein the first sensor and the second sensor are configured to obtain signals from adjacent tracks of the plurality of tracks of the storage medium, the signals being associated with data stored at the adjacent tracks. According to further embodiments of the present invention, a storage device and a method of reading data from a storage medium including a plurality of tracks are also provided.

Abstract: A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.

Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.

Abstract: The inventive concepts provide magnetic memory devices. The device includes a first magnetic pattern provided in one united body on a substrate and having a plurality of through-holes, a plurality of second magnetic patterns spaced apart from each other on the first magnetic pattern, a tunnel barrier between the first magnetic pattern and the second magnetic patterns, top electrodes disposed on the second magnetic patterns, respectively, and a plurality of plugs electrically connecting the top electrodes to the substrate through the through-holes, respectively.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first crystalline magnetic region, in one embodiment comprising Co and Fe. In one embodiment, the first electrode comprises a second amorphous region comprising amorphous XN, where X is one or more of W, Mo, Cr, V, Nb, Ta, Al, and Ti. In one embodiment, the first electrode comprises a second region comprising Co, Fe, and N.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: In one embodiment, a magnetic head includes a lower magnetic shield layer positioned at a media-facing surface, a pinned layer positioned above the lower magnetic shield layer at the media-facing surface, at least two MR elements extending in an element height direction by a first length positioned above the pinned layer and separated in a cross-track direction by an inner layer, bias layers extending in the element height direction by a second length positioned on outside edges of the MR elements and the pinned layer, and current paths positioned above and in electrical communication with the bias layers on either side of the inner layer, each current path extending in the element height direction away from the media-facing surface by a third length.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.

Abstract: One embodiment of a nonvolatile memory cell comprises a substrate having a surface, a bidirectional current switch comprising a first electrode, a second electrode, and a semiconductor layer disposed between the first and second electrodes, and a magnetoresistive element having a direct contact with the bidirectional current switch and comprising a free ferromagnetic layer having a reversible magnetization direction, a pinned ferromagnetic layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free and pinned ferromagnetic layers, wherein the magnetization direction of the free ferromagnetic layer is reversed by a bidirectional spin polarized current running through the magnetoresitive element in a direction perpendicular to the substrate surface, and wherein a magnitude of the spin polarized current is controlled by the bidirectional current switch. Other embodiments are described and shown.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.

Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer has a magnetic thermal stability coefficient having a plurality of magnetic thermal stability coefficient phases. A first phase magnetic thermal stability coefficient has a first slope below a first temperature. A second phase magnetic thermal stability coefficient has a second slope above the first temperature and below a second temperature greater than the first temperature. The first and second slopes are unequal at the first temperature. The magnetic thermal stability coefficient is zero only above the second temperature. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction.