Abstract: An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.

Abstract: According to one embodiment, a semiconductor substrate device includes a plurality of memory elements formed on the top surface of a semiconductor substrate, interlayer insulating films buried between the adjacent memory elements, a protection film formed on sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements, and contacts formed in the interlayer insulating films. The protection film includes a first protection film formed on the sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements and a second protection film formed on the first protection film. The first protection film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second protection film is made of a boron film or a boron nitride film.

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.

Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness or an amorphous ferromagnetic layer of Co40Fe40B20 of approximately 15 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: A method of manufacturing a magnetic tunnel junction device includes a barrier layer forming step of forming a tunnel barrier layer. The barrier layer forming step comprises a step of depositing a first metal layer, an oxygen surfactant layer forming step of forming an oxygen surfactant layer on the first metal layer, a step of deposing a second metal layer above the first oxygen surfactant layer, and an oxidation step of oxidizing the first metal layer and the second metal layer to form a metal oxide layer.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.

Abstract: A memory element is provided that includes a ferromagnetic (FM) layer having one or more ferromagnetic materials. One or more first molecule layers are positioned on the FM layer where charge transfer and interface chemistry between the one or more first molecule layers and FM layer induces a magnetic moment in the one or more first molecule layers. The magnetic moment is stored in the one or more first molecule layers acting as bit information that is retained or written into the one or more first molecule layers. One or more spin-filter layers are positioned on the one or more first molecule layers. The one or more spin-filter layers are positioned on the one or more spin-filter layers to form a physical or a chemical ?-dimer layer structure.

Abstract: Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.

Abstract: A magnetic pinned layer is formed over a substrate. An insulating film is formed over the magnetic pinned layer. A recess is formed in and through the insulating film. A tunneling insulating film is formed over a bottom of the recess. A first magnetic free layer is formed over the bottom of the recess via the tunneling insulating film. A second magnetic free layer is formed over the insulating film and made of a same material as the first magnetic free layer. A non-magnetic film is formed on sidewalls of the recess, extending from the first magnetic free layer to the second magnetic free layer and made of oxide of the material of the first magnetic free layer. An upper electrode is disposed over the first magnetic free layer, non-magnetic film and second magnetic free layer, and electrically connected to the first magnetic free layer and second magnetic free layer.

Abstract: A device includes a magnetic tunnel junction (MTJ) structure and a cap layer in contact with the MTJ structure. The device also includes a spin-on material layer in contact with a sidewall portion of the cap layer and a conducting layer in contact with at least the spin-on material layer and a portion of the MTJ structure. The cap layer has been etched to expose a portion of an electrode contact layer of the MTJ structure. The conducting layer is in electrical contact with the exposed portion of the electrode contact layer of the MTJ structure.

Abstract: A kind of growth method of Fe3Nin the MOCVD system, comprising following process: 1) make the surface nitridation of sapphire substrate; 2) pump in carrier gas N2, ammonia and organic gallium sources, and grow low temperature GaN buffer on substrate; 3) raise temperature and grow the GaN supporting layer; 4) pump in FeCp2 as Fe sources, then grow Fe3N on the GaN supporting layer; the Fe3N granular films and the Fe3N single crystal films are obtained.

Abstract: A magnetic semiconductor material contains at least one type of transition metals (Mn2+, Fe3+, Ru3+, Re2+, and Os3+) having five electrons in the d atomic orbital as a magnetic ion, in which the magnetic semiconductor material exhibits n-type electrical conduction by injection of an electron carrier and p-type electric conduction by injection of a hole carrier. A specific example is a layered oxy-pnictide compound represented by LnMnOPn (wherein Ln is at least one type selected from Y and rare earth elements of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and Pn is at least one selected from pnicogen elements of N, P, As, Bi, and Sb). A high-sensitivity magnetic sensor, current sensor, or memory device can be made by using a magnetic pn homojunction structure made of thin films composed of the magnetic semiconductor material.

Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Abstract: A magnetoresistive Wheatstone-bridge structure includes a magnetoresistive ring structure. The magnetoresistive ring structure includes a first magnetic layer comprising a ferromagnetic material. A second magnetic layer also includes a ferromagnetic material. A non-magnetic spacer is positioned between the first magnetic layer and the second magnetic layer. A vacant open region is positioned in the center region of the magnetoresistive ring structure. A plurality of magnetic states can exist in either the first magnetic layer or second magnetic layer. Furthermore, the magnetoresistive Wheatstone-bridge structure includes a plurality of voltage and current contacts arranged symmetrically upon the magnetoresistive ring structure. The magnetic state of the ring is detected by measuring its resistance.

Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

Abstract: A magnetic memory includes a first magnetic line, an electrode, a write-in portion, a second magnetic line, and a spin-wave generator. The first magnetic line has a plurality of magnetic domains and domain walls, the domain wall separating the magnetic domain. The electrode is provided to both ends of the first magnetic line. The write-in portion is provided adjacent to the first magnetic line. The second magnetic line is provided so that the second magnetic line intersects with the first magnetic line. The spin-wave generator provided to one end of the second magnetic line. The spin-wave detector provided to the other end of the second magnetic line.

Abstract: According to one embodiment, a semiconductor device, includes a magneto resistive element including a first magnetic layer, a first interface magnetic layer, a nonmagnetic layer, a second interface magnetic layer and a second magnetic layer as a stacked structure in order; and a metal layer including first metal atoms, second metal atoms and boron atoms, the metal layer being provided at least one region selected from under the first magnetic, between the first magnetic layer and the first interface magnetic layer, between the second interface magnetic layer and the second magnetic layer, and upper the second magnetic layer.

Abstract: The present disclosure provides a magnetoresistive random access memory (MRAM) device. The MRAM device includes a magnetic tunnel junction (MTJ) stack on a substrate; and a dual-layer passivation layer disposed around the MTJ stack. The dual-layer passivation layer includes an oxygen-free film formed adjacent sidewalls of the MTJ stack; and a moisture-blocking film formed around the oxygen-free film.

Abstract: A memory includes an underlying layer of a ferromagnetic body, a first nonmagnetic layer on the underlying layer, a data memorizing layer laid on the first nonmagnetic layer and made of a ferromagnetic body having perpendicular magnetic anisotropy, a reference layer coupled through a second nonmagnetic layer with the data memorizing layer, and first and second magnetization fixed layers laid underneath the underlying layer to come into contact with the underlying layer. The data memorizing layer includes a magnetization liberalized region having reversible magnetization, and overlapping with the reference layer, a first magnetization fixed region coupled with an end of the magnetization liberalized region, and having a magnetization direction fixed to +z direction by the first magnetization fixed layer, and a second magnetization fixed region coupled with a different end of the magnetization liberalized region, and having a magnetization direction fixed to ?z direction by the second magnetization fixed layer.

Abstract: The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer.

Abstract: The present disclosure provides a MTJ stack for an MRAM device. The MTJ stack includes a pinned ferromagnetic layer over a pinning layer; a tunneling barrier layer over the pinned ferromagnetic layer; a free ferromagnetic layer over the tunneling barrier layer; a conductive oxide layer over the free ferromagnetic layer; and a oxygen-based cap layer over the conductive oxide layer.

Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.

Abstract: According to one embodiment, a magnetoresistive element comprises a first magnetic layer, in which a magnetization direction is variable and is perpendicular to a film surface, a tunnel barrier layer that is formed on the first magnetic layer, and a second magnetic layer that is formed on the tunnel barrier layer, a magnetization direction of the second magnetic layer being variable and being perpendicular to the film surface. The second magnetic layer comprises a body layer that constitutes an origin of perpendicular magnetic anisotropy, and an interface layer that is formed between the body layer and the tunnel barrier layer. The interface layer has a permeability higher than that of the body layer and a planar size larger than that of the body layer.

Abstract: According to one embodiment, a magnetoresistive effect element includes a first magnetic film having magnetic anisotropy and an invariable magnetization direction in a direction perpendicular to a film plane, a second magnetic film having magnetic anisotropy and a variable magnetization direction in the direction perpendicular to the film plane, and a nonmagnetic film between the first magnetic film and the second magnetic film. At least one of the first and second magnetic films includes a first magnetic layer. The first magnetic layer includes a rare earth metal, a transition metal, and boron.

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry. At least one switching asymmetry balance layer (SABL) near the free layer of the MTJ reduces a first switching current Ic(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current Ic(ap-p) without increasing the average switching current of the device. The SABL may be a non-magnetic switching asymmetry balance layer (NM-SABL) and/or a magnetic switching asymmetry balance layer (M-SABL).

Abstract: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor.

Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a first memory region; and a second memory region. The transistor controls a conduction of each of a current flowing between the first and the second signal lines and an opposite current. The first memory region has a first magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and the magnetization direction becomes antiparallel when a current in another direction. The second memory region has a second magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and becomes antiparallel when a current flows in another first direction.

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract: A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form an MTJ cell, and forming a dielectric cap layer over a top surface and on a sidewall of the MTJ cell. The step of patterning and the step of forming the dielectric cap layer are in-situ formed in a same vacuum environment. A plasma treatment is performed on the dielectric cap layer to transform the dielectric cap layer into a treated dielectric cap layer, whereby the treated dielectric cap layer improves protection from H2O or O2, and thus degradation.

Abstract: A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form a MTJ stack, and forming a first dielectric cap layer over a top surface and on a sidewall of the MTJ stack. The step of patterning and the step of forming the first dielectric cap layer are in-situ formed in a same vacuum environment. A second dielectric cap layer is formed over and contacting the first dielectric cap layer.

Abstract: A magnetic memory device includes a first fixing layer, a first tunnel barrier coupled to the first fixing layer, a free layer coupled to the first tunnel barrier and having a stacked structure including a first ferromagnetic layer, an oxide tunnel spacer, and a second ferromagnetic layer, a second tunnel barrier coupled to the free layer, and a second fixing layer coupled to the second tunnel barrier.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed to one side of the MTJ. The induction line is configured to induce a perpendicular magnetic field at the MIJ.

Abstract: A magneto-electronic device includes a first electrode, a second electrode spaced apart from the first electrode, and an electric-field-controllable magnetic tunnel junction arranged between the first electrode and the second electrode. The electric-field-controllable magnetic tunnel junction includes a first ferromagnetic layer, an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. The first and second ferromagnetic layers have respective first and second magnetic anisotropies that are alignable substantially parallel to each other in a first state and substantially antiparallel in a second state of the electric-field-controllable magnetic tunnel junction.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two different directions. A symmetrical programming current switches the magnetization of the free region to either of the two different directions using a substantially similar current magnitude. In some embodiments, the STT-MRAM cell includes two fixed regions, each having fixed magnetizations in opposite directions and a free region configured to be switched in magnetization to be either parallel with or antiparallel to the magnetization of one of the fixed regions. Switching the free region to different magnetization directions may involve directing the programming current through one of the two oppositely magnetized fixed regions.

Abstract: A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls.

Abstract: An example embodiment relates to a method of forming a pattern structure, including forming an object layer on a substrate, and forming a hard mask on the object layer. A plasma reactive etching process is performed on the object layer using an etching gas including a fluorine containing gas and ammonia (NH3) gas together with oxygen gas to form a pattern. The oxygen gas is used for suppressing the removal of the hard mask during the etching process.

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

Abstract: The magnetic tunnel junction device of the present invention includes a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer formed between the first ferromagnetic layer and the second ferromagnetic layer. The insulating layer is composed of fluorine-added MgO. The fluorine content in the insulating layer is 0.00487 at. % or more and 0.15080 at. % or less. This device, although it includes a MgO insulating layer, exhibits superior magnetoresistance properties to conventional devices including MgO insulating layers. The fluorine content is preferably 0.00487 at. % or more and 0.05256 at. % or less.

Abstract: Disclosed is a magnetic tunnel junction structure having perpendicular anisotropic free layers, and it could be accomplished to reduce a critical current value required for switching and maintain thermal stability even if a device is fabricated small in size, by maintaining the magnetization directions of the free magnetic layer and the fixed magnetic layer constituting the magnetic tunnel junction structure perpendicular to each other.

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

Abstract: A fabrication method includes forming a spin-polarizing layer, a spin transport layer on the spin polarizing layer on a substrate, a free layer magnet on the spin transport layer, a non-magnetic layer on the spin polarizing layer, a reference layer on the non-magnetic layer, and a hard mask layer on the reference layer, etching the hard mask layer and forming a read portion including the reference layer, the nonmagnetic layer and the free layer magnet, forming a nonlinear resistor layer on surfaces of the spin transport layer, the spacers, and the hard mask layer, etching the nonlinear resistor layer, the spin transport layer, and the spin polarizing layer and forming a write portion including the spin transport layer and the spin polarizing layer, forming an interlevel dielectric layer, forming a trench, exposing an upper surface of the reference layer of the read and write portions.