With Source And Drain On Same Level And Without Cell Select Transistor (epo) Patents (Class 257/E21.682)
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Patent number: 9633747Abstract: Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The data I/O unit selectively drives a first global I/O line and first/second global I/O lines according to the first or second test modes. The data transmitter selectively transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line, and the data on the first and second global I/O lines onto the first and second local I/O lines according to the first or second test modes.Type: GrantFiled: March 18, 2013Date of Patent: April 25, 2017Assignee: SK hynix Inc.Inventor: Sang Kwon Lee
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Patent number: 9583558Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.Type: GrantFiled: February 17, 2016Date of Patent: February 28, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
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Patent number: 9406689Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.Type: GrantFiled: October 2, 2013Date of Patent: August 2, 2016Assignee: QUALCOMM INCORPORATEDInventors: Xia Li, Bin Yang, Seung Hyuk Kang
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Patent number: 9361982Abstract: A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.Type: GrantFiled: January 26, 2015Date of Patent: June 7, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Luca Milani, Fabrizio Torricelli, Anna Richelli, Luigi Colalongo, Zsolt Miklos KovĂ cs-Vajna
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Patent number: 9337048Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.Type: GrantFiled: September 23, 2014Date of Patent: May 10, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching-Hsiung Lee, Shih-Chang Tsai
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Patent number: 9293469Abstract: A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer.Type: GrantFiled: November 26, 2014Date of Patent: March 22, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Zhongshan Hong
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Patent number: 9281426Abstract: Certain exemplary embodiments can provide a method, which can comprise fabricating a system. The system can comprise a light amplification element and a charge transport element. Each of the light amplification element and a charge transport element can comprise one or more of a graphene layer, graphene oxide, graphene nano platelets, functionalized graphene, graphene/superconductor composite, tubular shaped nano carbon, semiconductor powder, thin film, nano wire, and nano rod.Type: GrantFiled: September 30, 2012Date of Patent: March 8, 2016Inventors: Khe C Nguyen, Hieu Dinh
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Patent number: 8963229Abstract: A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.Type: GrantFiled: September 18, 2012Date of Patent: February 24, 2015Assignee: Floadia CorporationInventors: Yutaka Shinagawa, Hideo Kasai, Yasuhiro Taniguchi
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Patent number: 8906765Abstract: A method of making a non-volatile double-gate memory cell. A gate of the control transistor is formed with a relief on a substrate. A control gate of the memory transistor is formed with a layer of a semiconductor material covering relief. The method includes chemical mechanical polishing (CMP) so as to strip, above the relief another layer and part of the layer of a semiconductor material; stripping of the remaining other layer on both sides of the relief, etching of the layer of a semiconductor material so as to strip this material above the relief and to leave only a pattern on at least one sidewall of the relief.Type: GrantFiled: January 8, 2013Date of Patent: December 9, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventor: Christelle Charpin-Nicolle
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Patent number: 8865548Abstract: A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face.Type: GrantFiled: January 8, 2013Date of Patent: October 21, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Christelle Charpin-Nicolle, Eric Jalaguier
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Patent number: 8558303Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.Type: GrantFiled: September 23, 2011Date of Patent: October 15, 2013Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Seunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Patent number: 8507971Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.Type: GrantFiled: August 6, 2008Date of Patent: August 13, 2013Assignee: Spansion LLCInventor: Satoshi Torii
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Patent number: 8502296Abstract: A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.Type: GrantFiled: July 7, 2008Date of Patent: August 6, 2013Assignee: National Semiconductor CorporationInventors: Andre P. Labonte, Jiankang Bu, Mark Rathmell
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Patent number: 8476691Abstract: A high voltage power semiconductor device includes high reliability-high voltage junction termination with a charge dissipation layer. An active device area is surrounded by a junction termination structure including one or more regions of a polarity opposite the substrate polarity. A tunneling oxide layer overlays the junction termination area surrounding the active device area in contact with the silicon substrate upper surface. A layer of undoped polysilicon overlays the tunneling oxide layer and spans the junction termination area, with connections to an outer edge of the junction termination structure and to a grounded electrode inside of the active area. The tunneling oxide layer has a thickness that permits hot carriers formed at substrate upper surface to pass through the tunneling oxide layer into the undoped polysilicon layer to be dissipated but sufficient to mitigate stacking faults at the silicon surface.Type: GrantFiled: February 18, 2011Date of Patent: July 2, 2013Assignee: Microsemi CorporationInventors: Dumitru Sdrulla, Duane Edward Levine, James M. Katana, Martin David Birch
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Patent number: 8470704Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.Type: GrantFiled: August 10, 2012Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Lee, Woon-Kyung Lee
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Patent number: 8446011Abstract: Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.Type: GrantFiled: September 23, 2011Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 8349686Abstract: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. Avoid part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto.Type: GrantFiled: August 3, 2011Date of Patent: January 8, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nitta
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Patent number: 8330204Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.Type: GrantFiled: June 21, 2011Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Yoshio Ozawa
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Patent number: 8319277Abstract: A semiconductor device that includes multiple logic circuit cells having respective logic circuits formed therein and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.Type: GrantFiled: January 22, 2010Date of Patent: November 27, 2012Assignee: Fujitsu LimitedInventors: Hideki Kitada, Takahiro Kimura
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Patent number: 8310008Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.Type: GrantFiled: July 27, 2010Date of Patent: November 13, 2012Assignee: Spansion LLCInventor: Burchell B. Baptiste
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Patent number: 8203178Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.Type: GrantFiled: August 20, 2010Date of Patent: June 19, 2012Assignee: Spansion LLCInventors: Ashot Melik Martirosian, Zhizheng Liu, Mark Randolph
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Patent number: 8076710Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming multiple conductive patterns 13a, forming an intermediate insulating film 16 on all of device isolation insulating films 6 and the conductive patterns 13a, forming a second conductive film 17 on the intermediate insulating film 16, patterning the second conductive film 17, the intermediate insulating film 16, and the multiple conductive patterns 13a, individually, to make the conductive patterns 13a into floating gates 13c and to make the second conductive film 17 into multiple strip-like control gates 17a. In the method, an edge, in a plan layout, of at least one of each of the conductive patterns 13a and each of the device isolation insulating films 6 is bent in a region between the control gates 17a adjacent in a row direction.Type: GrantFiled: August 17, 2009Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Hiroki Sugawara
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Patent number: 8063430Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.Type: GrantFiled: October 20, 2008Date of Patent: November 22, 2011Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Seunghun Hong, Sung Myung, Jiwoon Im, Minbaek Lee
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Patent number: 8008704Abstract: To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto.Type: GrantFiled: February 17, 2009Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nitta
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Patent number: 8004031Abstract: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.Type: GrantFiled: July 13, 2009Date of Patent: August 23, 2011Assignee: Micron Technology, Inc.Inventor: Seiichi Aritome
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Patent number: 7968407Abstract: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.Type: GrantFiled: April 1, 2010Date of Patent: June 28, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Albert Fayrushin
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Patent number: 7919823Abstract: A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area. The layout pattern of the second wiring bodies is the same as the layout pattern of the first wiring bodies. The cell well contact area comprises cell well contacts that have the same dopant type as the cell well and that function as source/drain regions of dummy transistors formed in the cell well contact area.Type: GrantFiled: March 3, 2010Date of Patent: April 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Kikuko Sugimae, Masayuki Ichige
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Patent number: 7910436Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.Type: GrantFiled: June 25, 2010Date of Patent: March 22, 2011Assignee: Actel CorporationInventor: John McCollum
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Patent number: 7897458Abstract: Provided is a method of forming a floating gate, a non-volatile memory device using the same, and a method of fabricating the non-volatile memory device, in which nano-crystals of nano-size whose density and size can be easily adjusted, are synthesized using micelles so as to be used as the floating gate of the non-volatile memory device. The floating gate is fabricated by forming a tunnel oxide film on the semiconductor substrate, coating a gate formation solution on the tunnel oxide film in which the gate formation solution includes micelle templates into which precursors capable of synthesizing metallic salts in nano-structures formed by a self-assembly method are introduced, and arranging the metallic salts on the tunnel oxide film by removing the micelle templates, to thereby form the floating gate.Type: GrantFiled: March 25, 2008Date of Patent: March 1, 2011Assignee: Kookmin University Industry Academy Cooperation FoundationInventors: Jaegab Lee, Jang-Sik Lee, Chi Young Lee, Byeong Hyeok Sohn
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Patent number: 7883984Abstract: A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photoresist pattern and the gate poly as a mask, wherein the ion implantation process forms a source/drain junction on the semiconductor substrate, forming a recess common source region in the trench by using a second photoresist pattern, and performing an ion implantation process on the recess common source region.Type: GrantFiled: November 18, 2009Date of Patent: February 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Ji-Hwan Park
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Patent number: 7842570Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.Type: GrantFiled: June 12, 2008Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Albert Fayrushin, Byung-Yong Choi, Choong-Ho Lee
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Patent number: 7804123Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.Type: GrantFiled: December 18, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Shoichi Watanabe
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Patent number: 7804125Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.Type: GrantFiled: July 24, 2007Date of Patent: September 28, 2010Assignee: Spansion LLCInventors: Ashot Melik Martirosian, Zhizheng Liu, Mark Randolph
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Patent number: 7795668Abstract: A semiconductor device includes a pair of selective gate lines formed above a semiconductor substrate, plural word lines formed above the substrate, plural contact plugs located between the selective gate lines, a first insulator formed in the trenches between the word lines, the first insulator including a first insulating film having a first upper surface flush with the substrate surface, a second insulator formed in the trenches between the contact plugs and including second and third insulating films, and a boro-phosphor-silicate glass film formed on the third insulating film and between the contact plugs. The second insulating film is of a kind same as the first insulating film. The third insulating film has a higher resistance to a wet etching process than the second insulating film. An interface between the second and third insulating films is located between a bottom and an upper end of the trench.Type: GrantFiled: July 2, 2007Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Matsuno
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Patent number: 7791126Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.Type: GrantFiled: December 22, 2006Date of Patent: September 7, 2010Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe Cina, Lorenzo Todaro
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Patent number: 7749841Abstract: A method of fabricating a nonvolatile semiconductor memory device includes the steps of: (a) forming a layered dielectric film on the semiconductor substrate; (b) forming a first conductive film on the layered dielectric film; (c) forming a first dielectric film on the first conductive film; (d) patterning the first dielectric film and the first conductive film to form a layered pattern composed of first dielectric films and first conductive films; and (e) implanting a first impurity along a direction having an inclination angle to a normal direction to a principal plane of the semiconductor substrate by using the layered pattern as a mask to form a first impurity diffusion layer being the same in conductivity type as the semiconductor substrate, wherein, step (d) includes patterning the first dielectric film to form the first dielectric films having a shape with a width narrower in an upper surface than in a lower surface.Type: GrantFiled: August 29, 2007Date of Patent: July 6, 2010Assignee: Panasonic CorporationInventor: Masatoshi Arai
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Patent number: 7723188Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.Type: GrantFiled: November 19, 2008Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Gyun Kim, Ji-Hoon Park, Sang-Woo Kang, Sung-Woo Park
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Patent number: 7713819Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.Type: GrantFiled: April 24, 2007Date of Patent: May 11, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Mutsumi Okajima
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Patent number: 7709380Abstract: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed.Type: GrantFiled: December 22, 2006Date of Patent: May 4, 2010Assignee: IMECInventor: Anabela Veloso
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Patent number: 7696074Abstract: A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.Type: GrantFiled: June 2, 2006Date of Patent: April 13, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jum Soo Kim, Jung Ryul Ahn
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Patent number: 7666740Abstract: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR type nonvolatile semiconductor memory device can be improved.Type: GrantFiled: September 13, 2007Date of Patent: February 23, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
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Publication number: 20100025750Abstract: A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 ?.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Applicant: MACRONIX International Co., Ltd.Inventors: Yao-Fu Chan, Ta-Kang Chu, Jung-Chuan Ting, Cheng-Ming Yih
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Patent number: 7626864Abstract: Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.Type: GrantFiled: April 26, 2006Date of Patent: December 1, 2009Inventor: Chih-Hsin Wang
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Patent number: 7618876Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.Type: GrantFiled: September 16, 2005Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
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Publication number: 20090261397Abstract: An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Applicants: QIMONDA FLASH GMBH, QIMONDA AGInventors: Josef Willer, Franz Hofmann, Michael Specht, Christoph Friederich, Doris Keitel-Schulz, Lars Bach, Thomas Melde
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Patent number: 7605036Abstract: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) filling the grooves formed on the floating gate-forming layer with masking materials; and (e) patterning the floating gate-forming layer, using the masking materials filling the grooves as an etching mask.Type: GrantFiled: December 20, 2006Date of Patent: October 20, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7595239Abstract: A method of fabricating a non-volatile memory device forming a first polysilicon film over a semiconductor substrate; forming a mitigation film over the first polysilicon film; forming a mask film over the mitigation film; etching the mask film, the mitigation film, and the first polysilicon film to form a first trench that defines first and second floating gates; forming an interlayer film over the mask film, the interlayer film filling the first trench to form a vertical structure; anisotropically etching the vertical structure of the interlayer film to form second and third trenches, the second trench being provided between the first floating gate and the etched vertical structure, the third trench being provided between the second floating gate the and etched vertical structure; forming a dielectric film over the first and second floating gate and the vertical structure, the dielectric film coating sidewalls of the second and third trenches; and forming a control gate layer over the dielectric film, the cType: GrantFiled: April 26, 2006Date of Patent: September 29, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jae Chul Om
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Patent number: 7585755Abstract: A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.Type: GrantFiled: October 30, 2007Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-hwan Song, Yoon-dong Park, June-mo Koo, Suk-pil Kim, Jae-woong Hyun, Choong-ho Lee, Tae-hun Kim
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Patent number: 7582559Abstract: A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.Type: GrantFiled: October 14, 2005Date of Patent: September 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-Joon Yeo, Won-Jun Lee, Tae-Hyun Kim, Ji-Hong Kim, Byoung-Moon Yoon
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Patent number: 7579246Abstract: An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle ?0 is defined as a tilt angle obtained by tilting a virtual plane perpendicular to the substrate and including an edge of the active region, toward the resist pattern by using as a fulcrum a point on the substrate nearest to the resist pattern, until the virtual plane contacts the resist pattern. The ion implantation is performed in a direction having a tilt angle larger than ?0 and allowing ions passed through the uppermost edge of the resist pattern to be incident upon an area between the resist pattern and the active region, and is not performed along a direction allowing the ions to be incident upon the active region.Type: GrantFiled: September 22, 2006Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Takuji Tanaka