Abstract: A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield.

Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: A semiconductor module manufacturing method includes a step of bonding a semiconductor wafer, which has a plurality of semiconductor elements each of which has an element electrode formed thereon, on an expansible first insulating resin layer; a step of dicing the semiconductor wafer; a step of expanding the first insulating resin layer to widen a gap between semiconductor elements; a pressure-bonding step of pressure-bonding a metal plate whereupon an electrode is arranged and the semiconductor elements with the widened gaps in between, by having a second insulating resin layer in between, and electrically connecting the electrode and the element electrodes; a step of forming a wiring layer which corresponds to each semiconductor element by selectively removing the metal plate and forming a plurality of semiconductor modules connected by the first insulating resin layer and the second insulating resin layer; and a step of separating the semiconductor modules by cutting the first insulating resin layer and th

Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

Abstract: An integrated circuit package system including: providing a substrate having a support mounted thereover; mounting an integrated circuit die above the substrate; mounting a wire-bonded die offset above the integrated circuit die creating an overhang supported by the support; connecting the wire-bonded die to the substrate with bond wires; and encapsulating the integrated circuit die, the wire-bonded die and the bond wires with an encapsulation.

Abstract: Provided is a semiconductor package. The semiconductor package includes a bonding wire electrically connecting a first package substrate and a second package substrate to each other and an insulating layer adhering the first package substrate and the second package substrate to each other and covering a portion of the bonding wire.

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.

Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Abstract: The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires.

Abstract: A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.

Abstract: An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.

Abstract: An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create a design restriction that has the potential to limit cooling capability.

Abstract: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.

Abstract: An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract: Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto.

Abstract: A packaged integrated circuit is provided comprising a first semiconductor die, a second semiconductor die, and a bonding wire. The first semiconductor die has a first internal bonding pad electrically connected to the package. The second semiconductor die has a second internal bonding pad located in an internal portion of the second semiconductor die. The second internal bonding pad is electrically connected to the first internal bonding pad through the first bonding wire.

Abstract: A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.

Abstract: A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Abstract: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower package by pillar-like members.

Abstract: In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.

Abstract: A pre-packaged structure includes a substrate with a substrate circuit, a die having a core circuit and disposed on the substrate, a passivation selectively covering the core circuit, a buffer metal layer electrically connected to the core circuit and completely covering the passivation and a copper wire bond electrically connected to the buffer metal layer and the substrate circuit.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.

Abstract: A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12, a second metal 16 provided in the resin 12 over the first metal 14, and being exposed on an upper surface of the resin 12, and a first wire 18 coupling the first semiconductor chip 10 to the first metal 14 and the second metal 16. The first wire 18 is coupled to the first metal 14 and the second metal 16 so as to be sandwiched therebetween.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.

Abstract: An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.

Abstract: A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

Abstract: In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.

Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: A flat chip package comprises an encapsulation body, a plurality of connecting fingers, a plurality of conductive lines, a chip, a plurality of bond wires and an insulation layer. The conductive lines, the chip, and the bond wires are encapsulated in the encapsulation body. The connecting fingers comprise a ground finger, a power finger and at least one signal finger. One side of the connecting fingers adheres to a surface of the encapsulation body, the other side of the connecting fingers is left exposed. The conductive lines comprise a ground line connected to the ground finger, and a power line connected to the power finger. The chip comprises a ground pin, a power pin and at least one signal pin. The bond wires connect the connecting fingers, the conductive lines and the chip. The insulation layer is printed on the surface of the encapsulation body except for the connecting fingers.

Abstract: It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 ?m in thickness.

Abstract: A semiconductor device in which overall thickness is reduced by suppressing the rising of a metal thin line and connection reliability is enhanced at the joint of metal thin line and other member during resin sealing. A method for manufacturing such semiconductor device is also provided. The semiconductor device (10A) comprises electrodes (12A, 12B, 12C), a semiconductor chip (13) bonded to the upper surface of the electrode (12A) formed in the shape of island, a metal thin line (15A) connecting the semiconductor chip (13) and the electrode (12C), a metal thin line (15B) connecting the semiconductor chip (13) and the electrode (12B), and a sealing resin (11) supporting those elements mechanically by sealing them integrally. The metal thin lines (15A, 15B) have planar shape curved convexly toward the upstream of the flow if the sealing resin (11) to be injected.

Abstract: An integrated circuit module comprises a chip, the chip comprising a substrate with a first main area and a second main area, the first main area comprising two half-sets of pads, the chip further comprising an integrated circuit with components and two half-sets of connection lines, the connection lines connecting the components of the integrated circuit to the pads, the integrated circuit further comprising a changeover device, the changeover device having two switching states in order to interchange the electrical assignment between the half-sets of the connection lines and the half-sets of the pads, and a carrier, the carrier comprising contact pieces. The chip is arranged on the carrier with one of the two main areas of the chip facing the carrier and the contact pieces of the carrier are connected to the pads of the chip, wherein one of the two switching states of the changeover device is selected, depending on which of the two main areas of the chip is the area facing the carrier.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: Provided is a semiconductor apparatus that reduces on-resistance in wiring between a first electrode terminal and a second electrode terminal. The semiconductor apparatus includes the first electrode terminal, the second electrode terminal, and at least two wires that connect the first and second electrode terminals. At least two wires are electrically connected with each other by using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode, for example. The second electrode terminal is a terminal of a source electrode of a MOSFET, for example.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor die, a bond pad formed on the semiconductor die, the bond pad comprising aluminum (Al), a bonding material comprising gold (Au) coupled to the bond pad, the bonding material covering at least a portion of the bond pad, and a wire coupled to the bonding material, the wire comprising copper (Cu). Other embodiments may be described and/or claimed.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.