Abstract: A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.

Abstract: A method is described having the steps of providing a surface having a plurality of wire bondable locations; wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.

Abstract: Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit includes a plurality of connection pads on at least one side of the integrated circuit, which connection pads can be coupled electrically conductingly by means of a respective bond wire, wherein in at least an edge area on the side of the integrated circuit, on which the connection pads are arranged, a support frame portion is arranged which is configured such that bond wires adjacent to each other can be supported on the support frame portion at a distance from each other.

Abstract: The invention provides a semiconductor device package. The package includes a chip disposed on a supported board and a conductive path formed between the chip and the supported board, on the backside of the supported board, or on the chip, so that the conductive path does not have to go around a region where the chip is located. Accordingly, the dimensions of the semiconductor device package are reduced.

Abstract: A semiconductor device includes two or more semiconductor devices with bond pads that are electrically connected to the same, single surface of a plurality of leads. The two or more devices may include substantially centrally located bond pads or substantially identically arranged bond pads.

Abstract: A semiconductor device according to the present invention includes: an insulating substrate; a metal bonding member being disposed on the insulating substrate and having a porous region and a metal region, the porous region being provided with multiple pores therein and being adjacent to the metal region in a plane direction of the insulating substrate; a solder material impregnated into the pores; a semiconductor element disposed on the surface of the porous region in the metal bonding member; a bonding wire connected to the surface of the metal region in the metal bonding member. This makes it possible to provide a semiconductor device having improved electrical conductivity and thermal conductivity, and enabling the weight reduction.

Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Abstract: A downhole tool having at least one semiconductor device, including: a die; a bonding pad which is attached to the surface of the die; a bonding wire which is attached to the bonding pad; a bonding point which is formed on the bonding pad for connecting the bonding wire to the bonding pad; an encapsulating resin encapsulating the die and being provided with a cavity such that a connecting portion of the bonding point and the bonding pad is exposed out of the resin in the cavity; and a lid on the encapsulating resin to cover the cavity.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: The present invention relates to a high power IC (Integrated Circuit) semiconductor device and process for making same. More particularly, the invention encompasses a high conductivity or low resistance metal stack to reduce the device R-on which is stable at high temperatures while in contact with a thick aluminum wire-bond that is required for high current carrying capability and is mechanically stable against vibration during use, and process thereof. The invention further discloses a thick metal interconnect with metal pad caps at selective sites, and process for making the same.

Abstract: Provided are a semiconductor package and a method of forming a wire loop of the semiconductor package. The semiconductor package includes: at least one semiconductor chip; a lead frame including a plurality of leads; and a plurality of wire loops, the wire loops connecting an electrode pad of the semiconductor chip to the leads. Wire loops include: a ball connected to the electrode pad; a pressed part formed on an upper surface of the ball by pressing the wire to overlap two parts of the wire; a first wire part extending substantially horizontally from the pressed part and including at least a portion contacting an upper surface of the semiconductor chip; a second wire part extending at a downward incline from the first wire part; and a third wire part extending from the second wire part and including an end connected to one of the leads.

Abstract: Inner wire bond pads are formed within a peripheral region of a semiconductor chip and at least one bonding wire is attached to the inner wire bond pads. The semiconductor chip may be customized for a specific configuration of choice by wiring inner wire bond pads. Alternately, the bonding wires may be employed to reinforce a power network or a ground network. Further, the bonding wire may serve as a passive radio frequency (RF) component. In addition, the bonding wire may be used a heat conduction path to transfer heat from the semiconductor chip to the upper package housing.

Abstract: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.

Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.

Abstract: The present invention aims to reduce an exclusively-possessed area of each of bonding wires mounted over a wiring board, for coupling a power amplifying unit of a semiconductor chip and an antenna switch of a second semiconductor chip in a semiconductor device that configures an RF module. In the RF module, the first semiconductor chip and the second semiconductor chip are mounted side by side in a central area of the wiring board. The first semiconductor chip is formed with amplifier circuits and a control circuit and comprises a silicon substrate or a compound semiconductor substrate. On the other hand, the second semiconductor chip is formed with an antenna switch and comprises the silicon substrate or compound semiconductor substrate. Pads of the first semiconductor chip and pads of the second semiconductor chip are respectively electrically coupled to one another.

Abstract: A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Abstract: Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within the BGA package is in the wire bonds that couple the set of contacts to the IC. The techniques described herein shorten the wire bonds in order to reduce the amount of parasitic inductance. The techniques include extending traces from a subset of the contacts inward into the BGA package toward the IC mounted. The wire bonds then couple the traces to the IC, thereby electrically coupling the subset of contacts to the IC. The presence of the traces substantially reduces lengths of the wire bonds relative to wire bonds that directly couple the set of contacts to the IC.

Abstract: An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that is configured to face away from a mounting board, and an interior surface that is configured to face towards the mounting board. The leads are bent away from the exterior surface, and each of the leads have a first end coupled to an IC and a second end configured to pass through one of a plurality of mounting holes extending through the mounting board. The IC is coupled to the interior surface.

Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.

Abstract: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.

Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die.

Abstract: A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up of a SiO2 film 5 formed on Si 4, a BPSG film 6 formed on the SiO2 film 5, a SiN film 7 formed on the BPSG film 6, a Poly-Si film bonding pad 1 formed on the SiN film 7, and an Al wire 2 bonded on the Poly-Si film bonding pad 1. A pad surface average roughness 8 of the Poly-Si film bonding pad 1 can be reduced. Thus it is possible to reduce gaps between bonding surfaces of the Al wire 2 and the Poly-Si film bonding pad 1 and increase a bonding area, thereby improving wire bonding characteristics.

Abstract: A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength.

Abstract: A chip package structure and its fabrication method are disclosed. Method of electrically connecting a chip with plural different metal layers is utilized to replace the conventional method of connecting identical metal layer merely. Besides, the method of a protective layer directly set on the metal layer to cover the chip and the conductive connecting structure is different from the general method of coating the solder mask on the metal layer. Moreover, a carrier utilized for support makes lighter and thinner substrate be fabricated. The fabrication method is utilized to manufacture by using the fabrication process of present package manufacturing. No additional equipments and fabrication processes are needed so that the PCB production flow may be simplified to reduce the package cost.

Abstract: A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to circuits of the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each ball bond. The dummy bond pads are formed between adjacent bond pads and have a plurality of lands not connected to each other. The ball bonds may be connected to the bond pads in a zigzag configuration and are partially connected to the dummy bond pads. Accordingly, the pitch between bond pads is reduced while preventing short circuits between adjacent ball bonds.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series with the first bond wire. A third bond wire is disposed on the semiconductor substrate so that a mutual inductance between the second bond wire and the third bond wire at least partially cancels a mutual inductance between the first bond wire and the second bond wire.

Abstract: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate.

Abstract: An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region.

Abstract: A stackable semiconductor package is revealed, primarily comprising a chip carrier, a chip, and a plurality of bottom bump sets. The chip carrier has a plurality of stacking pads disposed on the top surface and a plurality of bump pads on the bottom surface. The chip is disposed on and electrically connected to the chip carrier. The bottom bump sets are disposed on the corresponding bump pads and each consists of a plurality of conductive pillars. Solder-filling gaps are formed between the adjacent conductive pillars for filling and holding solder paste so that the soldering area can be increase and the anchoring effect can be enhanced due to complicated the soldering interfaces to achieve higher soldering reliability and less cracks at the soldering interfaces.

Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.

Abstract: An audio power amplifier package includes a non-signal lead, a first non-signal pad, a second non-signal pad and a plurality of bonding wires. The first non-signal pad and the second non-signal pad are disposed on a substrate. The bonding wires connect the non-signal lead to the first non-signal pad and the second non-signal pad respectively.

Abstract: There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or equal to 100% thereof.

Abstract: A Ball Grid Array (BGA) integrated circuit package having (i) an additional dedicated ground ring on the package substrate which provides a reduced area return current loop path to reduce wire bond inductance; and/or (ii) ground wires positioned between adjacent input/output wires on the substrate which provide additional transient current paths among the input/output wires for improved characteristic impedance and cross talk control.

Abstract: The stacked semiconductor package includes a substrate having a plurality of connection pads; a first semiconductor chip disposed over the substrate, a plurality of first bonding pads disposed at an first of the first semiconductor chip, redistributions extending from the first bonding pads to the middle of the upper face; wires for electrically connecting the first bonding pads to the connection pads; and a second semiconductor chip disposed over the first semiconductor chip leaving the first bonding pads exposed, and a plurality of second bonding pads disposed over the second semiconductor chip body and connected to the redistributions in a flip-chip manner. The stacked semiconductor package with this structure has a decreased volume, thus making the stacked semiconductor package more compact.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: A semiconductor package is provided. The semiconductor package comprises a substrate having a top surface and a bottom surface, a first semiconductor chip having a plurality of bonding pad regions electrically connected to the substrate by a plurality of first bonding wires, a spacer tape covering the active surface of the first semiconductor chip excluding the plurality of bonding pad regions, and a second semiconductor chip mounted on the active surface of the first semiconductor chip with the spacer interposed.

Abstract: A semiconductor device includes a supporting base whereupon an electrode terminal is placed; an intermediate member mounted on said supporting base; a semiconductor element, a portion thereof being supported with said intermediate member, and placed on said supporting base; and a convex-shaped member which corresponds to the electrode terminal of said semiconductor element and placed on said supporting base or said intermediate member; wherein the electrode terminal of said semiconductor element and the electrode terminal of said supporting base are connected with a bonding wire.

Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.

Abstract: An integrated circuit die has a plurality of I/O cells disposed about its periphery, each I/O cell having an I/O bonding pad. A first group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the first group of I/O cells having an I/O pad disposed thereon and spaced at a first distance from the periphery of the die. A second group of I/O cells is disposed at the periphery of the die at locations away from corners of the die, each of the second group of I/O cells having an I/O pad disposed thereon and spaced at a distance from the periphery of the die more than the first distance, the distance increasing as a function of the proximity of each I/O cell to a corner of the die.

Abstract: Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die.

Abstract: A method is described having the steps of providing a surface having a plurality of wire bondable locations, wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape.

Abstract: A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity. In order to provide a space for disposing a chip, the dimension of the second cavity is larger than that of the first cavity, such that there is a step at the interlinking region between the first cavity and the second cavity. Additionally, a plurality of wire bonding pads are disposed on the first surface around the first cavity. A package structure comprising the packaging substrate and the application thereof are also provided in the present invention.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract: An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. A plurality of metal lines is deposited on the top of the first chip, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package.

Abstract: A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.