Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

Abstract: A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: An IC which includes a first circuit and a plurality of first paired terminals each including a first power supply terminal and a first GND terminal which are connected to the first circuit, and a second circuit and a plurality of second paired terminals each including a second power supply terminal and a second GND terminal which are connected to the second circuit. The first and second paired terminals are isolated inside. A printed board with the IC mounted has an inductor which is provided in a route that guides a wiring line from the first GND terminal to the second GND terminal and the GND of the printed board. The printed board has a portion where each of the first GND terminals is arranged inside the terminal array of the IC. The inductor suppresses a high-frequency potential variation generated by the operation of the first circuit.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted.

Abstract: The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor.

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Abstract: A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively.

Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

Abstract: Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Abstract: In a semiconductor module, a first heat sink is disposed on a rear surface of a first semiconductor chip constituting an upper arm, and a second heat sink is disposed on a front surface of the first semiconductor chip through a first terminal. A third heat sink is disposed on a rear surface of a second semiconductor chip constituting a lower arm, and a fourth heat sink is disposed on a front surface of the second semiconductor chip through a second terminal. A connecting part for connecting between the upper arm and the lower arm is integral with the first terminal, and is connected to the third heat sink while being inclined relative to the first terminal.

Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.

Abstract: A semiconductor integrated circuit includes: a first conductive line coupled with a first pad for receiving a first voltage; a second conductive line coupled with a second pad for receiving a second voltage; a third conductive line arranged to be placed in a floating state; a first electrostatic discharge unit coupled between a third pad for inputting/outputting a signal and the third conductive line through a first common conductive line, wherein the first electrostatic discharge unit is configured to provide a bi-directional electrostatic discharge path between the third pad and the third conductive line according to an electrostatic discharge mode; a second electrostatic discharge unit coupled between the first conductive line and the third conductive line through a second common conductive line; and a third electrostatic discharge unit coupled between the second conductive line and the third conductive line through a third common conductive line.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: The invention discloses an array substrate, an LCD device, and a method for manufacturing the array substrate. The array substrate comprises scan line(s) and data line(s); the width of data line at the junction of the data line and the scan line is more than the width of the rest part of the data line. The invention can improve the final passed yield of LCD devices on the premise of not adding additional processes, and has the advantages of simple technology and low cost.

Abstract: A multi-layer film body comprises a plastic substrate strip conveyed in a first direction in a roll-to-roll process for printing electronic organic components on the substrate. A first electrically conducting layer is on the substrate, a semiconductor layer is on the first layer, an insulator layer is on the semiconductor layer and a second electrically conducting layer is on the insulator layer, the layers comprising a first interconnection assembly portion and a second electronic assembly portion successively positioned in the first direction, each portion comprising a central zone and a respective conductor tract input zone and conductor tract output zone bordering the respective central zones, the input, central and output zones of each portion each comprising parallel conductor tracts in the first conducting layer. Electrical connectors in the second conducting layer interconnect selected ones of the conductor tracts in the two portions.

Abstract: The semiconductor device comprises a semiconductor chip and a printed wiring board having a recess in which the semiconductor chip is housed face-down, wherein the printed wiring board comprises multiple wiring layers below a circuit surface of the semiconductor chip on which connection terminals are formed, and the multiple wiring layers include a first wiring layer for forming signal wires, a second wiring layer for forming a ground plane, and a third wiring layer for forming power wires and power BGA and ground BGA pads in sequence from the circuit surface.

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

Abstract: A power module includes a housing, a power semiconductor die enclosed within the housing and a first power terminal embedded in the housing and electrically connected to the power semiconductor die. A portion of the first power terminal protrudes outward from an external surface of the housing. The power module further includes a second power terminal embedded in the housing and electrically connected to the power semiconductor die and electrically insulated from the first power terminal. A portion of the second power terminal protrudes outward from the external surface of the housing by a distance less than the portion of the first power terminal so that the module has power connections with different heights.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: Disclosed herein are various embodiments of widebody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.

Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector.

Abstract: An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.

Abstract: A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die.

Abstract: A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: An integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. A method for forming an integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width.

Abstract: An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad.

Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Abstract: Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an “L” and mounting the package on a substrate. A horizontal portion of the bent lead-frame is about parallel with a surface of the package. A vertical portion of the bent lead frame is configured to extend the horizontal portion beyond the surface of the package. A device may be mounted between the substrate and the package.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: An integrated-circuit chip and external electrical connection elements are arranged on a first side of a substrate to form an assembly that is placed within a mold. The mold includes first and second opposed planar faces with a molding film made of a deformable material on the first planar face. The molding film is pressed against end faces of the external electrical connection elements. Encapsulating material then fills the mold cavity producing a semiconductor device that, when removed from the mold, includes electrical connection elements that are peripherally coated by the encapsulating material and have exposed end faces. An additional semiconductor device may be mounted over and in electrical connection with the electrical connection elements through the exposed end faces.

Abstract: A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad.

Abstract: A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.

Abstract: An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.

Abstract: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Abstract: A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.