Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.

Abstract: A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed.

Abstract: A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit.

Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

Abstract: A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having characteristics of a shaped platform removed; and an encapsulant around the conductive post and the integrated circuit device with the conductive post extending through the encapsulant and each end of the conductive post exposed from the encapsulant.

Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.

Abstract: A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.

Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.

Abstract: A silicon chip includes a silicon substrate, a plurality of pads, and a plurality of through vias to connect back-end-of-line wiring to the plurality of pads. The silicon substrate includes a layer of active devices and the back-end-of-line wiring connected to the active devices.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: There is provided a technology capable of reducing the mounting burden on the part of a customer which is a recipient of a package. Over a metal board, a single package and another single package are mounted together via an insulation adhesion sheet, thereby to form one composite package. As a result, as compared with the case where six single packages are mounted, the number of packages to be mounted is smaller in the case where three sets of the composite packages are mounted. This can reduce the mounting burden on the part of a customer.

Abstract: In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto.

Abstract: A method for manufacturing an integrated circuit package system includes: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant.

Abstract: A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells.

Abstract: A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.

Abstract: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes (1d) are formed in the centers of the signal coils (1b) of the silicon substrate (1a). Signal coils (2c) connected to solder balls (5) by way of through-conductors (2d) are formed on the interposer (2). Magnetic pins (3) that are composed of a magnetic material are inserted in the centers of the signal coils (1b and 2c).

Abstract: In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin and the second pin. The substrate includes a plurality of power domains and a power control unit. The second pin of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first pin of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.

Abstract: A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.

Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.

Abstract: Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port. The first portion of the trace is part of a transmission line having a characteristic impedance.

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include bottom surface portions which, in the completed semiconductor package, are exposed and at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body in the completed semiconductor package. The semiconductor package also includes one or more power bars and/or one or more ground rings which are integral portions of the original leadframe used to fabricate the same.

Abstract: An IC package includes an IC die mounted on a substrate that includes an ESD protection structure formed within the substrate to dissipate any charge accumulation associated with the package's no-connect pins resulting from human body model ESD and/or voltage spikes during package testing. For some embodiments, the ESD protection structure includes a resistive element formed in the substrate between the no-connect pin and a power plane. For other embodiments, the ESD protection structure includes a conductive ring formed in the substrate and laterally surrounding the land pad of the no-connect pin.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

Abstract: The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of the free wheeling diode are bonded and mounted on a circuit pattern formed on the main surface of the first substrate, and that a circuit pattern, which is so formed on the main surface of the second substrate as to oppose a surface electrode of the switching power semiconductor element and a surface electrode of the free wheeling diode, is connected to the surface electrodes of the switching power semiconductor element and the free wheeling diode through connective conductors to be soldered, respectively.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a device having a conductor with ends exposed on opposite sides of the device; forming a first surface depression on the device around the conductor; connecting a first component over the conductor and surrounded by the first surface depression; and applying a first underfill between the first component and the device, the first underfill substantially filled within a perimeter of the first surface depression.

Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.

Abstract: Disclosed is a method for detecting a mechanical fault state of a semiconductor arrangement, using a temperature profile.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component.

Abstract: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

Abstract: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Abstract: An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.

Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

Abstract: Provided is a semiconductor package including a first package and a second package. The first package includes a first substrate having a first front side and a first back side opposing the first front side. The first package further includes a first semiconductor chip on the first front side and an external connection member on the first semiconductor chip. The external connection member may be configured to electrically connect the first semiconductor chip to an external device. The second package includes a second substrate having a second back side facing the first back side of the first substrate and a second front surface opposing the second back side. The second package includes a second semiconductor chip on the second front side. The semiconductor package further includes an internal connection member between the first back side and the second back side to electrically connect the first package to the second package.

Abstract: A power semiconductor circuit has a power semiconductor module (2) embodied as a flat assembly. A particularly compact and space-saving production of a power semiconductor circuit may be achieved with the possibilities provided by an embodiment of the power semiconductor module, whereby the power semiconductor module (2) is arranged directly on a top track (3) of a power supply and/or output tracking (11) and a cooling device (5) is integrated in the tracking (11).

Abstract: The semiconductor device includes a silicon interposer made of a semiconductor and a first semiconductor chip mounted on one surface of the silicon interposer. The semiconductor device is provided with a through electrode penetrating the silicon interposer and having a side surface insulated from the silicon interposer; and a wiring connecting one end of the through electrode and the silicon interposer. The through electrode is connected to a power supply wiring or a GND wiring provided on the first semiconductor chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die.