Abstract: A universal substrate for semiconductor packages and the package are revealed. The universal substrate comprises a substrate core, two peripheral rows of bonding fingers and a central row of redistribution fingers disposed on the substrate core, and a solder mask formed on the substrate core. The redistribution fingers are located between two rows of the bonding fingers. The solder mask has an opening to expose the redistribution fingers. A plurality of exhaust grooves are formed on the solder mask without penetrating through the solder mask where one end of the exhaust grooves connects to the opening and the other end extends toward the edges of the substrate core without connecting to another opening exposing the bonding fingers to be the releasing channels of gases generated during die-attaching processes. When disposing larger IC chips, the issue of residue bubbles trapped in the covered opening and the issue of contaminations of bonding fingers by the die-bonding adhesives can be eliminated.

Abstract: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. By matching the wire line size in the flexible bridge to the size of circuits and/or signal pads on the chip and on the second component, the system allows signals to be sent between the circuits on the chip and the second component without having to change the scale of the interconnect, thereby alleviating wireability and bandwidth limitations of conventional chip packaging technologies.

Abstract: A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first end suitable for mounting to a PCB and which has a width. The package is also formed with a leadframe which includes a heat sink and ground plane blade suitable for connection to a bus bar, a plurality of connector leads suitable for connection to a PCB and at least one source tab lead suitable for connection to a module connector of such a control module. The plurality of connection leads and the source tab lead extend from the first end of the package housing side by side in the direction along and within the width of the first end of the package housing.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: A resin containing conductive particles and a gas bubble generating agent is supplied between a first substrate and a second substrate, and then the resin is heated to generate gas bubbles from the gas bubble generating agent contained in the resin so that the resin is self-assembled between electrodes. Then, the resin is further heated to melt the conductive particles contained in the resin, thereby forming connectors between electrodes. A partition member sealing the gap between the substrates is provided near a peripheral portion of the resin, and gas bubbles in the resin are discharged to the outside through the peripheral portion of the resin where the partition member is absent.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a shaped platform with a conductive post; mounting the shaped platform with the conductive post over a temporary carrier; mounting an integrated circuit device over the temporary carrier; encapsulating the conductive post and the integrated circuit device; removing a portion of the shaped platform isolating the conductive post; and removing the temporary carrier.

Abstract: A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed.

Abstract: A stacked structure of integrated circuits having spacer elements includes a substrate, a spacer element, a lower-layer integrated circuit, an upper-layer integrated circuit, and a molding layer. The substrate includes an upper surface on which the spacer element and the lower-layer integrated circuit are arrayed with each other. The lower-layer integrated circuit includes a solder-pad region and a non-solder-pad region adjacent to the spacer element. The upper-layer integrated circuit is disposed on the spacer element, and covers partly over the non-solder-pad region of the lower-layer integrated circuit. Therefore, the overall height of the stacked structure of integrated circuits can be lowered, making the packaging process simplified, the manufacturing process more stable, and the yield rate of production will be raised.

Abstract: The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface.

Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.

Abstract: Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin (sealing resin) provided so as to cover the semiconductor chip and the film. As a result, deterioration in contact property with the sealing resin is suppressed and a high frequency characteristic can be enhanced.

Abstract: According to one embodiment of the present invention, a semiconductor device is provided, that includes a semiconductor carrier; a cavity formed within the semiconductor carrier, the cavity extending from the top surface of the semiconductor carrier into the semiconductor carrier; and at least one semiconductor chip provided within the cavity.

Abstract: The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously.

Abstract: An apparatus that reduces parasitic capacitance in a MEMS device includes a dielectric layer on the surface of a silicon-on-insulator (SOI) substrate, a conductor embedded in the substrate and disposed between the dielectric layer and a buried oxide layer, and surface conductors on the dielectric layer and coupled to ends of the embedded conductor. A boundary region surrounds the embedded conductor and separates an inner region and an outer region of substrate, providing a p-n junction between the boundary region and the outer region of SOI substrate which is reverse biased to electrically isolate the inner region from the outer region of SOI substrate. An amplifier has an input connected to one end of the embedded conductor and an output connected to the inner region of the substrate. The amplifier senses a voltage at the input and produces a voltage that approximates the voltage at the output.

Abstract: Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a socketless manner or using a socket. The electrically conductive fluid interconnect may include, for example, a metal, an electrically conductive paste, or an electrically conductive polymer material. The fluid may be in a liquid or paste state over at least part of an operating temperature range of the IC device, and in other embodiments the fluid may be in the liquid or paste state at room temperature. Other embodiments are described and claimed.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.

Abstract: A semiconductor device is composed of a power supply interconnection extending from a certain starting point in a first direction and also extending from the starting point in a second direction orthogonal to the first direction, a plurality of power pads, and connecting interconnections providing electrical connection between the power supply interconnection and the power pads. The power supply interconnection, the power pads, and the connecting interconnections are arranged in a symmetrical manner with respect to a symmetry line crossing the starting point and extending in a direction at an angle of 45 degree to the first and second directions.

Abstract: Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

Abstract: A melting temperature adjustable metal thermal interface material (TIM) and a packaged semiconductor including thereof are provided. The metal TIM includes about 20-98 wt % of In, about 0.03-4 wt % of Ga, and at least one element of Bi, Sn, Ag and Zn. The metal TIM has an initial melting temperature between about 60-144° C.

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.

Abstract: A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal. At least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).

Abstract: A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a plurality of first line segments. Each of the first line segments connects adjacent first bumps. The first stripes are arranged in a second direction and connected to the power route. The ground route is disposed at one side of the power route in a third direction, and comprises a plurality of second bumps and a plurality of second line segments. Each of the second line segments connects adjacent second bumps. The second stripes, are arranged in a forth direction and connected to the ground route. The first stripes and the second stripes are interleaved without intersecting one another.

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

Abstract: The present invention alters the frequency response of an optoelectronic device to match a driver circuit that drives the optoelectronic device. The optoelectronic device is formed on a first substrate. A matching circuit is also formed on the first substrate and coupled to the optoelectronic device to change its frequency response. The matching circuit provides a precise and repeatable amount of inductance to an optoelectronic device.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.

Abstract: The semiconductor device, including an electrode formed on the surface of a semiconductor element; and a metallic ribbon connected to the electrode. The metallic ribbon has a depressed portion on a surface contacting to the electrode, and the metallic ribbon is connected to the electrode in such a state that the metallic ribbon is deformed toward the inside of the depressed portion.

Abstract: A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.

Abstract: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

Abstract: Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Abstract: A semiconductor device comprises a plurality of semiconductor constructions being mutually laminated each having a semiconductor substrate and a plurality of external connection electrodes arranged on the semiconductor substrate respectively, an insulating layer formed around the peripheries of the semiconductor constructions, an upper layer insulating film formed on an uppermost one of the semiconductor constructions and the insulating layer, and upper layer wirings arranged on the upper layer insulating film by electrically connecting to the external connection electrodes of semiconductor constructions.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

Abstract: A power module for low voltage applications, which does not include an insulated metal substrate is disclosed. The module includes a power shell and a plurality of lead frames each lead frame including a conductive pad on which one or more MOSFETs may be electrically mounted. The MOSFETs are electrically connected via wire bonds.

Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a wiring formed on the semiconductor chip; a passivation film, coating the wiring and having an opening for partially exposing the wiring from the passivation film; an interposing film, formed on a portion of the wiring facing the opening; and a post bump, raisedly formed on the interposing film and with a peripheral edge portion thereof protruding more toward a side than a peripheral edge of the interposing film.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a second integrated circuit device over the first integrated circuit device includes: attaching the second integrated circuit device to a first substrate side of a substrate, and connecting a first electrical interconnect between the second integrated circuit device and a second substrate side of the substrate through an opening in the substrate. The mountable integrated circuit package system further including: forming a package encapsulation over the first integrated circuit device and the carrier with the substrate partially exposed.

Abstract: A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other.

Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.

Abstract: The present invention relates to a power semiconductor device comprising a switching power semiconductor element, and a free wheeling diode in anti-parallel connection to the switching power semiconductor element. The power semiconductor is characterized in that a reverse electrode of the switching power semiconductor element and a reverse electrode of the free wheeling diode are bonded and mounted on a circuit pattern formed on the main surface of the first substrate, and that a circuit pattern, which is so formed on the main surface of the second substrate as to oppose a surface electrode of the switching power semiconductor element and a surface electrode of the free wheeling diode, is connected to the surface electrodes of the switching power semiconductor element and the free wheeling diode through connective conductors to be soldered, respectively.

Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: A power semiconductor device is disclosed. In one embodiment, the power semiconductor device includes a plurality of device components that are contact-connected by bonding wires having different thicknesses. The surface of at least one bonding wire serves as a contact area for at least one further bonding wire, the bonding wire that serves as contact area being thicker than the bonding wire contact-connected thereon.