Abstract: A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A liquid epoxy resin composition for semiconductor encapsulation comprising: (A) an epoxy resin, (B) an imidazole compound, and (C) a maleimide compound, a semiconductor device encapsulated by the liquid epoxy resin composition, and an assembly in which a cured material of the liquid epoxy resin is positioned between a printed circuit substrate and a semiconductor die. The liquid epoxy resin composition provides a cured material that has an excellent adhesiveness to a semiconductor chip surface and has an excellent moisture resistance.

Abstract: An image sensor module having a light gathering region and a light non-gathering region includes an image sensor, a light blocking spacer, a lens layer and a fixing shell. The light blocking spacer is disposed on the image sensor and located in the light non-gathering region. The light blocking spacer has a through hole exposing a portion of the image sensor in the light gathering region. The lens layer is disposed on the light blocking spacer and covers the through hole. The lens layer includes a transparent substrate and a lens disposed on the transparent substrate and located in the light gathering region. The fixing shell located in the light non-gathering region wraps the sidewalls of the image sensor, the light blocking spacer and the lens layer continuously. The material of the fixing shell includes a thermosetting material. A method for manufacturing the image sensor module is also provided.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175-C is 2000 Pa or more.

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract: A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.

Abstract: A semiconductor device includes a semiconductor chip, and an encapsulation resin which covers and encapsulates the semiconductor chip, the semiconductor chip having a recess formed in the surficial portion thereof; the recess having, on the deeper side than a predetermined portion thereof, a portion having a larger width than the predetermined portion has; and the encapsulation resin being anchored in the recess.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a conductive bump formed over the substrate and a semiconductor die with an active surface oriented to the substrate. An encapsulant is deposited over the semiconductor die and the conductive bump, and the encapsulant is planarized to expose a back surface of the semiconductor die opposite the active surface while leaving the encapsulant covering the conductive bump. A channel is formed into the encapsulant to expose the conductive bump. The channel extends vertically from a surface of the encapsulant down through the encapsulant and into a portion of the conductive bump. The channel extends through the encapsulant horizontally along a length of the semiconductor die. A shielding layer is formed over the encapsulant and the back surface of the semiconductor die.

Abstract: A method for manufacturing a microelectronic assembly including stacked first and second microelectronic components having a cavity therebetween including defining said cavity by means of a lateral wall forming a closed frame extending around a determined area of the first component except for an opening used as a vent; forming within the closed frame and opposite to the vent an obstacle capable of forming, in cooperation with the lateral wall, a bypass duct for the filling material; performing a flip-chip hybridization of the first and second components, a surface of the second component resting on the upper edge or end of the lateral wall formed on the first component to form said at least one cavity; injecting the filling material in liquid form between the two hybridized components to embed said at least one cavity and to make it tight by obstruction of the vent as said filling material solidifies.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: Systems and methods for applying a thin layer of a liquid to the surface of a wafer with topography formed therein. The systems and methods include spreading a deposit of the liquid into a thin film on a wafer support, lowering the wafer onto the film, removing the wafer with an adhering layer of the film, positioning the wafer over a device wafer with the liquid film disposed between the wafers, curing the thin layer. The thin layer may be a UV adhesive which bonds the wafers upon exposure to UV light.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. The two metals may for an alloy of a predefined stoichiometry in at least two locations on either side of the midpoint of the raised feature. This alloy may have advantageous features in terms of density, mechanical, electrical or physical properties that may improve the hermeticity of the seal, for example.

Abstract: A semiconductor device has a first semiconductor die containing a low pass filter and baluns. The first semiconductor die has a high resistivity substrate. A second semiconductor die including a bandpass filter is mounted to the first semiconductor die. The second semiconductor die has a gallium arsenide substrate. A third semiconductor die including an RF switch is mounted to the first semiconductor die. A fourth semiconductor die includes an RF transceiver. The first, second, and third semiconductor die are mounted to the fourth semiconductor die. The first, second, third, and fourth semiconductor die are mounted to a substrate. An encapsulant is deposited over the first, second, third, and fourth semiconductor die and substrate. A plurality of bond wires is formed between the second semiconductor die and first semiconductor die, and between the third semiconductor die and first semiconductor die, and between the first semiconductor die and substrate.

Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base package carrier; mounting an interposer over the base package carrier; forming a base package encapsulation over the base package carrier and the interposer with the base package encapsulation having a cavity for exposing the interposer; and forming a support recess in the base package encapsulation between a non-horizontal edge of the base package encapsulation and the cavity.

Abstract: In a method of manufacturing a high-frequency module, a resin substrate with a high frequency circuit including an electronic component mounted thereon is placed so that the electronic component faces a resin bath. A resin which is in a non-flowable state in the resin bath is softened until the resin becomes flowable, and air in space formed between the resin substrate and the resin is sucked. The resin substrate is brought into contact with a liquid surface of the resin. The resin is pressurized and allowed to flow into a gap between the resin substrate and the electronic component. The resin is cured so that a resin portion is formed on the resin substrate. A shield metal film is formed on a surface of the resin portion.

Abstract: The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Abstract: A method of manufacturing includes arranging an integral resin sleeve formed by integrating a plurality of sleeve parts so that the sleeve parts are respectively fitted with a plurality of electrode terminals. There is a press-fitting of the sleeve parts to the electrode terminals by performing mold clamping on molds to apply a force downward on the integral resin sleeve. Further, there is a filling of a molding resin into a hollow cavity of the molds.

Abstract: A blank and a semiconductor device include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.

Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Abstract: Provided is a power semiconductor device including: an insulating substrate; a circuit pattern formed on an upper surface of the insulating substrate; a power semiconductor formed on the circuit pattern; a plurality of metal socket electrode terminals formed perpendicularly to the circuit pattern or the power semiconductor so as to be in conduction with external terminals; an integral resin sleeve in which a plurality of sleeve parts are integrated, the plurality of sleeve parts being fitted with the plurality of metal socket electrode terminals from above the plurality of metal socket electrode terminals and having openings at both ends thereof; and a molding resin covering the insulating substrate, the circuit pattern, the power semiconductor, the electrode terminals, and the integral resin sleeve.

Abstract: The method for producing a circuit substrate of the present invention is characterized in that the circuit substrate is produced using as sheet a circuit substrate sheet including an uncured layer a part of which, the part being other than a part at which a circuit chip is disposed, is selectively curable before or after disposal of said circuit chip, wherein the uncured layer has a softness that enables embedding of the circuit chip in the circuit substrate sheet upon pressing the circuit chip that has been disposed on a surface of the uncured layer. According to the method for producing the circuit substrate of the present invention, the circuit chip can be embedded inwards with high accuracy, and the circuit substrate can be produced easily with high accuracy.

Abstract: A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

Abstract: An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.

Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.

Abstract: An electrical and/or electronic device including: an electrical and/or electronic component; two layers of material forming front and back faces of the device and between which the electrical and/or electronic component is encapsulated, the component including at least two opposite faces placed facing the two layers of material; an electrical contact element placed in contact with one of the faces of the electrical and/or electronic component; an element based on at least one elastic material placed between one of the two layers of material and the electrical contact element, forming a first layer of elastic material covering the one of the two layers of material; and a second layer based on at least one elastic material with an elastic stiffness less than the stiffness of the elastic material in the first layer, placed in contact with the first layer of elastic material.

Abstract: The present invention relates to a photosensitive adhesive composition that has thermal press bondability to an adherent after being patterned by exposure and development and enables alkali development, wherein a storage elastic modulus at 110° C. after exposure and further heat curing is not less than 10 MPa.

Abstract: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.

Abstract: This invention discloses a device comprising multiple functional layers formed on substrates, wherein at least one functional layer comprises an electrical energy source. In some embodiments, the present invention includes an insert for incorporation into ophthalmic lenses that has been formed by the stacking of multiple functionalized layers.

Abstract: A manufacturing method for an encapsulated micromechanical component has the following steps: creating an intermediate substrate having a plurality of perforations; laminating an encapsulation substrate onto a front side of the intermediate substrate, which closes the perforations on the front side; laminating an MEMS functional wafer onto a rear side of the intermediate substrate; the MEMS functional wafer being aligned with the intermediate substrate in such a way that the perforations form cavities over the corresponding functional areas of the MEMS functional wafer.

Abstract: A semiconductor device includes a semiconductor chip in which an internal circuit is formed, with the internal circuit having an output signal that fluctuates due to variation of fluctuation in electrical characteristics of multiple circuit elements constituting the internal circuit; a chip tab on which the semiconductor chip is mounted, with the semiconductor chip completely overlapping the chip tab and the circuit elements in the semiconductor chip arranged on the chip tab, and encapsulation resin within which the semiconductor chip and the chip tab are sealed. A horizontal surface area of the chip tab is smaller than that of the semiconductor chip, and a distance between a periphery of the chip tab and a periphery of the semiconductor chip is sufficient to cause stress exerted on the semiconductor chip by the encapsulation resin to be uniform across the horizontal surface area of the chip tab.

Abstract: Disclosed is a method for manufacturing an electronic device, the method including: placing an electronic component on a substrate 11; forming standing portions 13 on the surface of the substrate 11 on which the electronic component 10 is placed, the standing portions 13 comprising a thermally decomposable resin; applying an encapsulating material 14 so as to encapsulate the electronic component 10 and cover around the standing portions 13 while exposing a portion of each of the standing portions 13 from the surface of the encapsulating material 14; heating the standing portions 13 to decompose and remove the standing portions 13, thereby forming holes 141 through the encapsulating material 14; and placing a conductive material 15 in the holes 141.

Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.

Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.

Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.

Abstract: A method of making a light emitting diode (LED) having an optical element is provided, comprising: providing a curable liquid polysiloxane/TiO2 composite, which exhibits a refractive index of >1.61 to 1.7 and which is a liquid at room temperature and atmospheric pressure; providing a semiconductor light emitting diode die having a face, wherein the semiconductor light emitting diode die emits light through the face; contacting the semiconductor light emitting diode die with the curable liquid polysiloxane/TiO2 composite; and, curing the curable liquid polysiloxane/TiO2 composite to form an optical element; wherein at least a portion of the optical element is adjacent to the face.

Abstract: The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges.

Abstract: A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned.

Abstract: A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.

Abstract: A curable liquid polysiloxane/TiO2 composite for use as a light emitting diode encapsulant is provided, comprising: a polysiloxane prepolymer with TiO2 domains having an average domain size of less than 5 nm, wherein the curable liquid polysiloxane/TiO2 composite contains 20 to 60 mol % TiO2 (based on total solids); wherein the curable liquid polysiloxane/TiO2 composite exhibits a refractive index of >1.61 to 1.7 and wherein the curable liquid polysiloxane/TiO2 composite is a liquid at room temperature and atmospheric pressure. Also provided is a light emitting diode manufacturing assembly.

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.

Abstract: There is provided a method for manufacturing a semiconductor device, including: forming an interconnection layer over a support base; mounting a plurality of semiconductor chips over the interconnection layer; molding the plurality of semiconductor chips with resin; forming an alignment mark in the resin; and obtaining a molded structure by removing the interconnection layer, the plurality of semiconductor chips and the resin from the support base after forming the alignment mark.