Abstract: Thin film photovoltaic devices are provided. The device includes a transparent substrate; a transparent conductive oxide layer on the transparent substrate; an n-type window layer on the transparent conductive oxide layer, an absorber layer on the n-type window layer, and a back contact layer on the absorber layer. The n-type window layer includes a plurality of nanoparticles spatially distributed within a medium, with the nanoparticles comprising cadmium sulfide. In one embodiment, the medium has an optical bandgap that is greater than about 3.0 eV (e.g., includes a material other than cadmium sulfide). Methods are also provided for such thin film photovoltaic devices.

Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.

Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract: Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.

Abstract: A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.

Abstract: A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.

Abstract: Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die.

Abstract: The invention pertains to a method for manufacturing a microelectronic device on a substrate comprising at least one first electrical component and one second electrical component distributed respectively in first and second levels stacked one on top of the other on the substrate, this method comprising: the manufacture of at least one first arm and one second arm of different lengths, each of these arms directly and mechanically linking an electrical pad to a fixed anchoring point on the substrate, and the electrical pad is made inside the first level and then shifted, prior to the electrical connection of the second component, to a position of connection wherein the upper face of the electrical pad is in contact with the interior of the second level parallel to the substrate.

Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.

Abstract: A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.

Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Abstract: A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

Abstract: A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.

Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.

Abstract: A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.

Abstract: Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip.

Abstract: A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract: A chip-stacked semiconductor package including a stacked chip structure including a plurality of separate chips stacked on each other; a flexible circuit substrate having the stacked chip structure mounted on a first side of the flexible circuit substrate in a first region of the flexible circuit substrate, and being electrically connected to at least one of the plurality of separate chips of the stacked chip structure by folding a second region of the flexible circuit substrate; a sealing portion sealing the stacked chip structure and the flexible circuit substrate; and an external connecting terminal on a second side of the flexible circuit substrate.

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements.

Abstract: A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.

Abstract: A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Abstract: A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers.

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die.

Abstract: A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed.

Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.