Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: An organic light emitting display device includes a substrate, a plurality of sub-pixels on the substrate, each sub-pixel including a first region configured to emit light and a second region configured to transmit external light, a plurality of thin film transistors disposed in the first region of the each sub-pixel, a plurality of first electrodes disposed in the first region of each sub-pixel and electrically connected to the thin film transistors, a first insulating layer on at least a portion of the first region of each sub-pixel to cover a portion of the first electrode, an organic emission layer on the first electrode, a second insulating layer on at least a portion of the second region of each sub-pixel, the second insulating layer including a plurality of openings therein, and a second electrode covering the organic emission layer, the first insulating layer, and the second insulating layer.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Abstract: A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction or horizontal direction; and wherein with the control unit, the size of the buffer transistor is equal to or greater than the pixel pitch in the scanning direction of the laser beam.

Abstract: An X-ray detector includes a substrate; a gate line that is extended in a first direction on the substrate; a gate electrode that is extended from the gate line; a semiconductor layer that is positioned on the gate electrode; a source electrode and drain electrode that are positioned on the semiconductor layer; a lower electrode that is extended from the drain electrode; a photodiode that is positioned on the lower electrode; a first insulation layer that is positioned on the source electrode and the drain electrode and that includes a first opening that exposes the source electrode; and a data line that is extended in a second direction intersecting a first direction on the first insulation layer to intersect the gate line with the first insulation layer interposed between the data line and the gate line, and the data line being electrically connected to the source electrode through the first opening.

Abstract: A liquid crystal display device with a built-in touch screen, which uses a common electrode as a touch-sensing electrode including an intersection of a gate line and a data line to define a pixel region, a bridge line disposed in a central portion of the pixel, an insulating layer formed on the bridge line, a first contact hole disposed through the insulating layer to expose a predetermined portion of an upper surface of the bridge line, a contact metal on the insulating layer and inside the first contact hole, the contact metal electrically connected with the bridge line, a first passivation layer on the contact metal, a second contact hole disposed through the first passivation layer to expose a predetermined portion of an upper surface of the contact metal, a common electrode on the first passivation layer and inside the second contact hole, a conductive line electrically connected with the common electrode, and a second passivation layer on the first passivation layer and the conductive line, wherein the

Abstract: A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.

Abstract: The present disclosure relates to a high light transmittance in-plan switching liquid crystal display device and a method for manufacturing the same. The liquid crystal display device includes: a substrate; a gate line disposed in horizontal direction on the substrate; a gate insulating layer covering the gate line; a data line disposed in vertical direction on the gate insulating layer; an additional insulating layer on the data line having same size and shape with the data line; a passivation layer covering the additional insulating layer; and a common electrode overlapping with the data line on the passivation layer. According to the present disclosure, the failure due to the parasitic capacitance and the load for driving the display panel are reduced and it is possible to make large and high definition display panel.

Abstract: A light-emitting element, a light-emitting module, a light-emitting panel, or a light-emitting device in which loss due to electrical resistance is reduced is provided. The present invention focuses on a surface of an electrode containing a metal and on a layer containing a light-emitting organic compound. The layer containing a light-emitting organic compound is provided between one electrode including a first metal, whose surface is provided with a conductive inclusion, and the other electrode.

Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.

Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.

Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.

Abstract: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate such that when the flexible printed circuit substrate and the thin film transistor array panel are connected to each other, the passivation layer having a porous structure and which is formed at the connection portion therebetween connects the flexible printed circuit substrate with the thin film transistor array panel thereby minimizing an exposed area of the metal of the connection portion to improve a corrosion resistance thereof.

Abstract: A light-emitting device is disclosed. More particularly, the light-emitting device comprises a first substrate; a light-emitting element over the first substrate; a second substrate over the light-emitting element, wherein the second substrate contains a concave portion; a sealant between the first substrate and the second substrate; and a material having a water absorbing property is formed in the concave portion, wherein the material having the water absorbing property is provided so as not to overlap the light-emitting element, and so as to be spaced from the sealant.

Abstract: A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: Provided are an organic light-emitting diode (OLED) display apparatus and a method of manufacturing the OLED display apparatus. Pixel-defining layers (PDLs) are formed of inorganic and organic insulating layers to minimize non-uniformities of the thicknesses of organic emission layers (OEMLs) and planarize lower thin film transistors (TFTs). Therefore, a lifespan of the OLED display apparatus is improved.

Abstract: A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

Abstract: A high-performance thin film transistor structure which is easily manufactured is provided. The thin film transistor structure includes: a first electrode; second and third electrodes apart from each other in a hierarchical level different from that of the first electrode; first, second, and third wirings connected to the first, second, and third electrodes, respectively; a main stack body disposed so as to be opposed to the first electrode with an interlayer insulating layer in between, between the first electrode, and the second and third electrodes; and a sub stack body including an insulating layer and a semiconductor layer, disposed so as to be opposed to the first wiring with the interlayer insulating layer in between, between the first and second wirings in a position where the first and second wirings overlap and/or between the first and third wirings in a position where the first and third wirings overlap.

Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.

Abstract: A solid-state imaging device includes a photoelectric conversion portion that is provided above an imaging surface of a substrate, and a plurality of readout circuit portions that are provided below the photoelectric conversion portion on the imaging surface. The photoelectric conversion portion includes a photoelectric conversion film that receives incident light and produces a signal charge, and a first electrode and a second electrode that sandwich the photoelectric conversion film, and the first electrode, the photoelectric conversion film, and the second electrode are sequentially layered upward on the imaging surface. Further, each of the readout circuit portions includes a readout circuit that is electrically connected with the first electrode and reads out the signal charge produced by the photoelectric conversion portion, and a ground electrode that is grounded, and the ground electrode is interposed between the readout circuit and the first electrode on the imaging surface.

Abstract: An embodiment of the present disclosure provides a method of manufacturing an array substrate, comprising at least a step of forming a TFT pattern in a pixel region and correspondingly forming a TFT testing pattern in a testing region, wherein before forming a passivation layer to cover the pixel region and the testing region, a step of removing a gate insulation layer thin film above a testing line lead in the TFT testing pattern.

Abstract: A mobility measuring apparatus includes a storage unit that respectively stores a relationship between the mobility ? of carriers in a semiconductor and a decay constant ? of the carriers and a relationship between a reflectivity R of the semiconductor to a terahertz light and the decay constant ? of the carriers, a light radiating unit that radiates a terahertz light to the semiconductor as a sample, a detecting unit that detects a reflected light of the sample to the radiated terahertz light, a reflectivity calculating unit that calculates the reflectivity Rexp of the sample by determining a ratio of an intensity of the reflected light relative to an intensity of the radiated terahertz light, an obtaining unit that obtains the decay constant ?exp of the sample corresponding to the reflectivity Rexp of the sample by making reference to the stored relationship between the reflectivity R and the decay constant ? of the carriers, and a mobility calculating unit that calculates the mobility ?exp of the sample fr

Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.

Abstract: A display device includes a first display panel including a common electrode disposed thereon, and a second display panel including; thin film transistors (“TFTs”) each including a gate electrode, a source electrode, and a drain electrode, a first passivation layer disposed on the source and drain electrodes, a second passivation layer disposed on the first passivation layer and including at least one sensing protrusion, pixel electrodes disposed on the second passivation layer and connected with the drain electrode, and at least one conductive member disposed on the sensing protrusion.

Abstract: A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.

Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.

Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.

Abstract: A substrate for a liquid crystal display device, including a pixel electrode formed on the substrate, wherein the pixel electrode includes a micro-cutout pattern defined by a plurality of micro-cutouts extending in four different directions with respect to an extension direction of a rough structural pattern. The substrate also includes a first electrode extending in a first direction, a second electrode extending in a second direction that is approximately perpendicular to the first direction, and a contact hole that electrically connects the pixel electrode and the first electrode. A portion of the rough structural pattern and/or a portion of the micro-cutout pattern overlap the first electrode. Also disclosed is a liquid crystal display device including such a substrate.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.

Abstract: An integrated circuit die includes a semiconductor substrate and a plurality of electronic circuits on the semiconductor substrate. The semiconductor substrate is divided into a plurality of regions. A first region of the substrate supports a first type of electronic circuit and has first permittivity, permeability, and conductivity characteristics. A second region of the substrate supports a second type of electronic circuit and has second permittivity, permeability, and conductivity characteristics.

Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.

Abstract: An organic EL display including a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.

Abstract: An array substrate for a display device and its fabrication method are disclosed. The array substrate for a display device includes: a gate wiring and a gate electrode connected to the wiring formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer and a barrier metal layer stacked with the gate insulating layer interposed therebetween on the gate electrode; a data wiring formed on the barrier metal layer and source and electrodes connected to the data wiring; a passivation film formed on the source and drain electrodes and the data wiring and having a contact hole exposing a portion of the drain electrode, the barrier metal layer and the active layer; and a pixel electrode formed on the passivation film and being in contact with the drain electrode and the barrier metal layer including the active layer.

Abstract: The present invention provides a thin film transistor (TFT) array substrate and a method for manufacturing the same. After depositing a first metal layer on a substrate, a first mask is utilized to form gate electrodes. After depositing a gate insulating layer and a semiconductor layer on the substrate, a second mask is utilized to pattern the semiconductor layer, so as to keep portions of the semiconductor layer above the gate electrodes. After depositing a transparent and electrically conductive layer and a second metal layer on the substrate, a multi tone mask is utilized to form source electrodes, drain electrodes, pixel electrodes and common electrodes. The present invention can simplify the manufacturing process thereof.

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract: A method includes forming a first gate stack over a portion of a fin, forming a dummy gate stack over the fin, growing an epitaxial material from exposed portions of the fin, forming a layer of dielectric material over the epitaxial material, the first gate stack, and the dummy gate stack, performing a planarizing process that removes portions of the layer of dielectric material, the first gate stack, and the dummy gate stack, pattering a first mask over portions of the layer of dielectric material and the dummy gate stack, forming a silicide material on exposed portions of the first gate stack, removing the first mask, pattering a second mask over portions of the layer of dielectric material and the first gate stack, removing a polysilicon portion of the dummy gate stack to define a cavity, removing the second mask, and forming a second gate stack in the cavity.

Abstract: A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

Abstract: A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.

Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Abstract: An electrooptical device substrate, contains: a first insulating film provided on a substrate; two or more pixels; a first concave portion provided in the first insulating film over the two or more pixels; a second concave portion provided on the bottom surface of the first concave portion; a thin film transistor containing an organic semiconductor layer provided in the second concave portion, a gate insulating film provided on the organic semiconductor layer, and a gate electrode provided on the gate insulating film and being matched to one pixel among the two or more pixels; a scanning line which is provided at an upper side with respect to the gate insulating film and provided in the first concave portion over the two or more pixels; and a data line electrically connected to the thin film transistor.

Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.

Abstract: A display substrate includes a transistor, a black matrix and a color spacer. The transistor is connected to a gate line, and a data line crossing the gate line. The black matrix includes a first light-blocking portion covering the gate line and the data line, and a second light-blocking portion covering a channel of the transistor. The second light-blocking portion has a thickness which is smaller than a thickness of the first light-blocking portion. The color spacer is disposed on the second light-blocking portion.

Abstract: A high-performance thin film transistor structure which is easily manufactured is provided. The thin film transistor structure includes: a first electrode; second and third electrodes apart from each other in a hierarchical level different from that of the first electrode; first, second, and third wirings connected to the first, second, and third electrodes, respectively; a main stack body disposed so as to be opposed to the first electrode with an interlayer insulating layer in between, between the first electrode, and the second and third electrodes; and a sub stack body including an insulating layer and a semiconductor layer, disposed so as to be opposed to the first wiring with the interlayer insulating layer in between, between the first and second wirings in a position where the first and second wirings overlap and/or between the first and third wirings in a position where the first and third wirings overlap.

Abstract: The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.