Energy Conversion Device (epo) Patents (Class 257/E27.123)
  • Patent number: 11777044
    Abstract: A solar module having at least two substring groups, each including an upper substring having solar cells connected in series and arranged in a matrix having two adjacent columns and a plurality of rows, and a lower substring having solar cells connected in series and arranged in a matrix having two adjacent columns and a plurality of rows. The lower and upper substrings include the same number of solar cells. A cross-connector interconnects the lower and upper substrings electrically in parallel forming the substring group. A bypass diode is arranged electrically in the cross-connector, and cross-connectors of each substring group are interconnected electrically in series. Two columns of the lower substring include a different number of solar cells and two columns of the upper substring include a different number of solar cells, such that the number of solar cells of the upper substring and of the lower substring is odd.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 3, 2023
    Assignee: HANWHA Q CELLS GMBH
    Inventors: Christian Gerbig, Marcel Kühne, Michael Mette
  • Patent number: 10741785
    Abstract: A reflective electrode, a method of manufacturing the reflective electrode, and an organic light emitting diode display including the reflective electrode are disclosed. The reflective electrode includes a first transparent conductive layer formed of a transparent conductive material, a reflective layer disposed on the first transparent conductive layer and including a plurality of grains formed of a reflective material, and a second transparent conductive layer disposed on the reflective layer and formed of a transparent conductive material. The adjacent grains are spaced from each other.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Donghee Yoo, Kyunghoon Lee, Taehan Park
  • Patent number: 10423027
    Abstract: A display device panel includes a display area including pixels and a non-display area. Each pixel is connected to one of gate lines and one of data lines. The non-display area includes data pad sections. The non-display area further includes a depiction of a first information code and a depiction of a second information code. The depiction of the first information code is disposed between first two adjacent data pad sections and is apart from an outline of the non-display area by a first distance. The depiction of the second information code is disposed between second two adjacent data pad sections and is apart from the outline of the non-display area by a second distance different from the first distance.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Young Lee, Sang Hyun Kang, Dae Hyun Kim, Seung Hwan Kim, Joo Yeol Lee, Jang Bog Ju
  • Patent number: 9818824
    Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Seung Yang, Eun Hye Choi, Sun Jung Kim, Seung Hun Lee, Hyun-Jung Lee
  • Patent number: 8975717
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 8969992
    Abstract: An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma E. Sosa Cortes, Wilfried E. Haensch, Steven J. Koester, Devendra K. Sadana, Katherine L. Saenger, Ghavam Shahidi, Davood Shahrjerdi
  • Patent number: 8883548
    Abstract: Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: John W. Sherohman, Jick Hong Yee, Arthur W. Combs, III
  • Patent number: 8835980
    Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Taro Itatani
  • Patent number: 8772894
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: July 8, 2014
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 8754424
    Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott D. Schellhammer, Vladimir Odnoblyudov, Jeremy S. Frei
  • Patent number: 8580599
    Abstract: Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 12, 2013
    Assignee: SunPower Corporation
    Inventors: Seung Bum Rim, Taeseok Kim, David D. Smith, Peter J. Cousins
  • Patent number: 8552519
    Abstract: In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built in and to reuse or repair them, two split modules 61 are arranged in series in a containing case 62 in a semiconductor module 60. In each split module 61, power generating semiconductor elements 1 arranged in a matrix of a plurality of rows and columns, and a conductive connection mechanism for connecting the plurality of semiconductor elements 1 in each row in series and the plurality of semiconductor elements 1 in each column in parallel are molded with transparent synthetic resin, and a connection conductor 67 is allowed to project at the end. A conductive waved spring 70 and an external terminal 76 are provided on the end side of the containing case 62, and series connection of the two split modules 61 is ensured by mechanical pressing force of the conductive waved spring 70.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 8, 2013
    Assignee: Kyosemi Corporation
    Inventor: Josuke Nakata
  • Patent number: 8436445
    Abstract: A method for processing a thin-film absorber material with enhanced photovoltaic efficiency includes forming a barrier layer on a soda lime glass substrate followed by formation of a stack structure of precursor layers. The method further includes subjecting the soda-lime glass substrate with the stack structure to a thermal treatment process with at least H2Se gas species at a temperature above 400° C. to cause formation of an absorber material. By positioning the substrates close together, during the process sodium from an adjoining substrate in the furnace also is incorporated into the absorber layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 7, 2013
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 8420517
    Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 16, 2013
    Assignee: Innovalight, Inc.
    Inventors: Giuseppe Scardera, Shihai Kan, Maxim Kelman, Dmitry Poplavskyy
  • Publication number: 20130049016
    Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Scott D. Schellhammer, Vladimir Odnoblyudov, Jeremy S. Frei
  • Patent number: 8383929
    Abstract: Under one aspect, a nonplanar photovoltaic module having a length includes: (a) an elongated nonplanar substrate; and (b) a plurality of solar cells disposed on the elongated nonplanar substrate, wherein each solar cell in the plurality of solar cells is defined by (i) a plurality of grooves around the nonplanar photovoltaic module and (ii) a groove along the length of the photovoltaic module. In some embodiments, each groove of the plurality of grooves about the photovoltaic module, independently, has a repeating pattern, a non-repeating pattern, or is helical. In some embodiments, the module further includes a patterned conductor providing serial electrical communication between adjacent solar cells. In some embodiments, portions of the patterned conductor providing serial electrical communication between adjacent solar cells are within a groove of the plurality of grooves about the photovoltaic module.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 26, 2013
    Assignee: Solyndra LLC
    Inventors: Erel Milshtein, Benyamin Buller
  • Patent number: 8349637
    Abstract: In a method for the production of a solar cell, a flat aluminium layer is applied to the back of a solar cell substrate. The aluminium is alloyed into the silicon substrate by the effect of the temperature and forms an aluminium BSF. The remaining aluminium that has not been alloyed into the silicon is subsequently removed. The aluminium BSF is transparent to light.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: January 8, 2013
    Assignee: Gebr. Schmid GmbH & Co.
    Inventors: Christian Schmid, Dirk Habermann
  • Patent number: 8343797
    Abstract: A process for preparing a solar cell comprising a support, a layer of cadmium sulfide (CdS), a layer of cadmium telluride (CdTe), a layer of a transparent conductive oxide (TCO), a conductive metallic layer and optionally a layer of buffer material, the CdS layer and the CdTe layer being deposited by means of a pulsed plasma deposition (PPD) method, a solar cell obtainable by means of the described process being also provided.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 1, 2013
    Inventors: Carlo Taliani, Petr Nozar
  • Patent number: 8329495
    Abstract: A method of forming a PV module includes forming conductors on a top surface of a PV coated substrate; forming insulators on the top surface of the PV coated substrate; and cutting the PV coated substrate to form a plurality of individual PV cells. The PV coated substrate is cut so that each of the PV cells has some of the conductors and an insulator on its top surface. Multiple PV cells are then joined to form a PV module by attaching an edge of a first one of the PV cells under an edge of a second one of the PV cells so that at least a portion of the conductors on the first PV cell electrically contacts a bottom surface of the second PV cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 11, 2012
    Assignee: Preco, Inc.
    Inventor: Chris Walker
  • Patent number: 8298852
    Abstract: A thin film type solar cell and a method for manufacturing the same is disclosed, which is capable of providing a wide light-transmission area without lowering cell efficiency and increasing processing time, so that the solar cell can be used as a substitute for a glass window in a building. The thin film type solar cell generally comprises a substrate; a plurality of front electrodes at fixed intervals on the substrate; a plurality of semiconductor layers at fixed intervals with a contact portion or separating channel interposed in-between, the plurality of semiconductor layers on the plurality of front electrodes; and a plurality of rear electrodes at fixed intervals by the each separating channel interposed in-between, the each rear electrode being electrically connected with the each front electrode; wherein the each rear electrode is patterned in such a way that a light-transmitting portion is included in a predetermined portion of the rear electrode.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: October 30, 2012
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Yong Woo Shin, Won Hyun Kim, Dae Yup Na, Hyun Jun Cho, Dong Woo Kang, Doo Young Kim, Hyun Kyo Shin, Cheol Hoon Yang
  • Publication number: 20120228609
    Abstract: It is disclosed that, as an embodiment, a test circuit includes a test signal supply unit configured to supply a test signal via a signal line to signal receiving units provided in a plurality of columns, wherein the test signal supply unit is a voltage buffer or a current buffer, and the test circuit has a plurality of test signal supply units and a plurality of signal lines, and wherein at least one test signal supply unit is electrically connected to one signal line different from a signal line to which another test signal supply unit is electrically connected.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 13, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Akira Okita, Masaaki Iwane, Yu Arishima, Masaaki Minowa
  • Patent number: 8241945
    Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Suniva, Inc.
    Inventors: Adam M. Payne, Daniel L. Meier, Vinodh Chandrasekaran
  • Publication number: 20120192913
    Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: AHMED ABOU-KANDIL, KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Publication number: 20120153423
    Abstract: The present invention relates to a silicon photomultiplier with trench isolation for maintaining the photon detection efficiency high while increasing the dynamic range, by reducing the degradation of the effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 21, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Joon Sung LEE
  • Publication number: 20120139074
    Abstract: Disclosed is an electronic apparatus in which a thermoelectric conversion element and at least one of a photoelectric conversion element and a transistor or a diode are monolithically integrated, or which prevents interference between a p-type thermoelectric conversion unit and an n-type thermoelectric conversion unit. This electronic apparatus includes a thermoelectric conversion element (100) including a semiconductor layer (38) which performs thermoelectric conversion and at least one of a photoelectric conversion element (102) in which at least a portion of the semiconductor layer (38) performs photoelectric conversion and a transistor (104) or a diode having at least a portion of the semiconductor layer (38) as an operating layer.
    Type: Application
    Filed: August 5, 2010
    Publication date: June 7, 2012
    Inventor: Masayuki Abe
  • Publication number: 20120133015
    Abstract: A photoelectric conversion element of the present invention comprises: a first semiconductor layer of a first conductivity type; a first electrode arranged on the back side of the first semiconductor layer a second semiconductor layer of a second conductivity type, the second semiconductor layer on the light-receiving side of the first semiconductor layer; a light-receiving face-side electrode provided on the light-receiving side of the second semiconductor layer; a second electrode arranged on the back side of the first semiconductor layer, and electrically separated from the first semiconductor layer, but connected to the second semiconductor layer; and a penetrating-connecting section penetrating the first semiconductor layer, and connecting the light-receiving face-side electrode with the second electrode, wherein the photoelectric conversion element is characterized in that the first electrode and the second electrode are arranged equidistantly apart from a central axis passing through a center of the ph
    Type: Application
    Filed: December 7, 2011
    Publication date: May 31, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Akiko TSUNEMI, Satoshi OKAMOTO
  • Publication number: 20120103402
    Abstract: An apparatus, system, and method are disclosed for providing optical power to a semiconductor chip. An active semiconductor layer of the semiconductor chip is disposed toward a front side of the semiconductor chip. The active semiconductor layer comprises one or more integrated circuit devices. A photovoltaic semiconductor layer of the semiconductor chip is disposed between the active semiconductor layer and a back side of the semiconductor chip. The back side of the semiconductor chip is opposite the front side of the semiconductor chip. The photovoltaic semiconductor layer converts electromagnetic radiation to electric power. One or more conductive pathways between the photovoltaic semiconductor layer and the active semiconductor layer provide the electric power from the photovoltaic semiconductor layer to the one or more integrated circuit devices of the active semiconductor layer.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Eric V. Kline
  • Publication number: 20120037960
    Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.
    Type: Application
    Filed: September 21, 2011
    Publication date: February 16, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Haruhisa YOKOYAMA, Hiroshi SAKOH, Kazuhiro YAMASHITA, Mitsuo YASUHIRA, Yuichi HIROFUJI
  • Publication number: 20120025342
    Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 2, 2012
    Applicant: Sol Chip Ltd.
    Inventors: Shani Keysar, Reuven Holzer, Ofer Navon, Ram Friedlander
  • Publication number: 20120017970
    Abstract: A method for forming solar cells includes providing a crystalline silicon substrate which can be mono-, multi-, or poly-crystalline, the substrate being defined by a first thickness, the substrate including a first surface and a second surface, the first surface on an opposite side of the second surface. The method also includes forming a separation region within the first thickness, the separation region including hydrogen species, the separating region being substantially parallel to the first surface, the separation region defining a first portion and a second portion within the thickness. Additionally, the method includes providing a mould structure defining a support region on the first surface in which a layer of ceramic material is formed, followed by mould removal. Additionally, the method includes forming electrical devices on the first portion and packaging formed solar cells, including interconnections for solar tile applications.
    Type: Application
    Filed: August 11, 2010
    Publication date: January 26, 2012
    Applicant: SILICON CHINA (HK) LIMITED
    Inventors: Nathan W. Cheung, Chung Chan
  • Patent number: 8053343
    Abstract: A method for forming a selective emitter of a solar cell and a diffusion apparatus for forming the same are provided. The method includes texturing a surface of a silicon substrate by etching the silicon substrate, coating an impurity solution on the surface of the silicon substrate, injecting a first thermal energy into the whole surface of the silicon substrate, and, while the first thermal energy is injected into the whole surface of the silicon substrate, injecting a second thermal energy by irradiating a laser beam into a partial region of the surface of the silicon substrate.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: November 8, 2011
    Assignee: SNT. Co., Ltd.
    Inventors: Yusung Huh, Seungil Park, Mangeun Lee
  • Patent number: 8034654
    Abstract: The method is disclosed that Si+ is implanted on Si substrate to enhance strain relaxation at the interface between the metamorphic GexSi1?x buffer layers and Si substrate, in order to facilitate the growth of a high quality Ge on Si substrate. And several GexSi1?x buffer layers (Si/Ge0.8Si0.2/Ge0.9Si0.1/Ge) are grown on top of Si substrate by UHVCVD. Then grow pure Ge layer of low dislocation density on GexSi1?x buffer layer. Finally, grow up high efficiency III-V solar cell on GexSi1?x buffer layer.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 11, 2011
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Shih-Hsuan Tang, Yue-Cin Lin
  • Publication number: 20110230006
    Abstract: An apparatus for fabricating thin films on substrate panels includes a deposition chamber enclosed by sidewalls, a lid, and a base. The apparatus includes a mixing chamber disposed above the lid and configured to receive vapor species and form a mixed vapor. The mixing chamber is coupled with the deposition chamber via inlets through the lid, including a diffuser plate. Two heater plates disposed side by side on the base supporting and heating two substrates.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 22, 2011
    Applicant: Stion Corporation
    Inventors: Robert D. Wieting, Kenneth B. Doering, Jurg Schmitzburger
  • Publication number: 20110155219
    Abstract: A thin film solar cell includes a substrate, a transparent electrode layer, a semiconductor layer, a back electrode layer, a positive electrode and a negative electrode. The semiconductor layer is formed on the transparent electrode layer and has grooves. The back electrode layer is formed on the semiconductor layer, in which formation of the semiconductor layer with the back electrode layer is patterned and the patterned formation with the transparent electrode layer form unit cells connected in series. The positive electrode is formed upon a front unit cell of the unit cells. The negative electrode is formed upon a last unit cell of the unit cells. The back electrode layer is formed to fill at least the grooves of the front unit cell and the last unit cell to directly connect with the transparent electrode layer. A method for fabricating a thin film solar cell is also provided.
    Type: Application
    Filed: December 12, 2010
    Publication date: June 30, 2011
    Applicant: Du Pont Apollo Limited
    Inventors: Jia-Wei Ma, Chan-Ching Chang, Yeong-Shyang Lee, Hi-Ki Lam
  • Patent number: 7932184
    Abstract: A method of manufacturing a solar cell module, including: forming a laminated body including a first protective member, a first sealing member having a first melting point, a plurality of solar cells, a second sealing member having a second melting point higher than the first melting point, and the second protective member; heating the first sealing member to a temperature equal to or higher than the first melting point but lower than the second melting point; and heating the second sealing member to a temperature equal to or higher than the second melting point. In forming the laminated body, the second sealing member is arranged to form a surface including a plurality of convex portions faces the first sealing member.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: April 26, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Yousuke Ishii
  • Publication number: 20110061715
    Abstract: Provided is a thin film photoelectric conversion device with maximized output characteristic, by improving an uneven current value of a photoelectric conversion cell caused by an uneven film thickness and an uneven film quality of a photoelectric conversion semiconductor layer, which may be generated in scaling up an integrated-type thin film photoelectric conversion device. The thin film photoelectric conversion device includes: a substrate, a transparent electrode layer, a photoelectric conversion unit, and a back electrode layer. An increasing rate ?Zt of the film thickness Zt of the transparent electrode layer along X and an increasing rate ?Zs of the film thickness Zs of the photoelectric conversion unit along X have different signs, whereas one line segment in a parallel direction to a main surface of the substrate is taken as X?.
    Type: Application
    Filed: May 19, 2009
    Publication date: March 17, 2011
    Applicant: KANEKA CORPORATION
    Inventors: Takashi Fujibayashi, Toshiaki Sasaki, Yuko Tawada
  • Patent number: 7855423
    Abstract: A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A first surface of the planar element is mounted to the substrate and is located to surround the semiconductor device such that the semiconductor device is aligned by the aperture. The mount further has means for mounting the semiconductor device to the substrate in an aligned position. Some embodiments include a method of making and/or using such a mount.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 21, 2010
    Assignee: SolFocus, Inc.
    Inventors: Stephen Horne, Gary D. Conley
  • Patent number: 7851249
    Abstract: A method for making a tandem solar cell includes the steps of providing a ceramic substrate, providing a titanium-based layer on the ceramic substrate, providing an n+-p?-p+ laminate on the titanium-based layer, passivating the n+-p?-p+ laminate, providing an n-i-p laminate on the n+-p?-p+ laminate, providing a p-type ohmic contact, providing an n-type ohmic contact providing an anti-reflection layer of SiCN/SiO2 on the n-i-p laminate.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 14, 2010
    Assignee: Atomic Energy Council - Institute of Nuclear Energy Research
    Inventors: Tsun-Neng Yang, Shan-Ming Lan, Chin-Chen Chiang, Wei-Yang Ma, Chien-Te Ku, Yu-Hsiang Huang
  • Publication number: 20100236606
    Abstract: A photoelectric conversion device wherein a lower electrode, a photoelectric-conversion semiconductor layer of a compound semiconductor material, and an upper electrode are formed in this order on an anodized substrate in which an anodized oxide film as an insulating film is formed on an aluminum base arranged at at least one surface of a metal substrate. The lower electrode is formed on the anodized oxide film. The main component of the photoelectric-conversion semiconductor layer is a compound semiconductor material with a chalcopyrite structure of Group Ib, IIIb and VIb elements. The photoelectric conversion device includes at least one insulative alkali supply layer formed between the anodized substrate and the lower electrode, and at least one insulative antidiffusion layer being formed between the anodized substrate and the at least one alkali supply layer, and suppressing diffusion, toward the anodized substrate, of one or more alkali and/or alkaline earth metal elements.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 23, 2010
    Applicant: FUJIFILM Corporation
    Inventors: Hiroyuki Kobayashi, Shinya Suzuki, Toshiaki Fukunaga, Atsushi Mukai
  • Patent number: 7795067
    Abstract: A method of manufacturing partially light transparent thin film solar cells generally includes forming a solar cell structure stack and forming multiple openings through the solar cell structure stack. The solar cell structure stack includes a flexible foil substrate, a contact layer formed over the flexible foil substrate, a Group IBIIIAVIA absorber layer formed over the contact layer and a transparent conductive layer formed over the Group IBIIIAVIA absorber layer. A terminal structure including at least one busbar and a plurality of conductive finger patterns is deposited onto a top surface of the transparent conductive layer forming a semi-transparent solar cell.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: September 14, 2010
    Assignee: Solopower, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20100218819
    Abstract: A semiconductor-based optoelectronic device such as a solar cell has an n-type layer and a p-type layer, together forming a p-n junction. Contact regions are formed on the device, with light-receiving regions between contact regions. A window layer is formed over the n-type layer or the p-type layer at the light-receiving region, the window layer promoting reduced carrier recombination at the surface of the n-type or p-type layer, and/or reflection of minority carriers in the n-type or p-type layer towards the p-n junction. The device has a window protection layer formed over the window layer, the window protection layer providing protection from degradation of the window layer during manufacture and/or operation of the device. For GaAs-based devices the window layer may be Al0.9Ga0.1As and the window protection layer may be GaAs. Additionally, an AlAs etch stop layer may be provided over the window protection layer.
    Type: Application
    Filed: October 6, 2008
    Publication date: September 2, 2010
    Applicant: The University Court of the University of Glasgow
    Inventors: Corrie Farmer, Colin Stanley
  • Publication number: 20100212728
    Abstract: To provide an electronic device employing a carbon nanostructure and exhibiting novel characteristics. n-Conduction-type carbon nanowalls 81 were formed on an n-conduction-type silicon substrate 80. Subsequently, p-conduction-type carbon nanowalls 82 were grown so as to cover the surfaces of the n-conduction-type carbon nanowalls 81. Gold was deposited on the end surfaces of the p-conduction-type carbon nanowalls 82 through EB deposition, to thereby form a first electrode 85. Separately, gold was deposited on the bottom surface of the n-conduction-type silicon substrate 80 through EB deposition, to thereby form a second electrode 86. Thus, there was formed a diode having a pn junction between the n-conduction-type carbon nanowalls 81 and the p-conduction-type carbon nanowalls 82.
    Type: Application
    Filed: September 28, 2006
    Publication date: August 26, 2010
    Inventors: Masaru Hori, Yutaka Tokuda, Hiroyuki Kano
  • Publication number: 20100147371
    Abstract: Energy harvesting devices including first nano-helixes amplifying incident electromagnetic waves, second nano-helixes inducing currents from the electromagnetic waves amplified by the first nano-helixes, and a diode rectifying induced currents generated by the second nano-helixes.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 17, 2010
    Inventor: Sung Nae Cho
  • Publication number: 20100139761
    Abstract: Provided are a dye-sensitized solar cell and a method of fabricating the same. The dye-sensitized solar cell includes a lower substrate, an upper substrate, a dielectric, a semiconductor electrode layer, a dye layer, and an electrolyte. The upper substrate is spaced from the lower substrate and has a light emitting surface facing a surface of the lower substrate and a light incident surface opposite to the light emitting surface. The dielectric is disposed on the surface of the lower substrate. The semiconductor electrode layer includes electrode dots disposed on the dielectric. The dye layer is disposed on surfaces of the electrode dots. The electrolyte is disposed between the lower substrate and the upper substrate.
    Type: Application
    Filed: August 24, 2009
    Publication date: June 10, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hogyeong Yun, Yongseok Jun, Mangu Kang, Hunkyun Pak, Jongdae Kim
  • Patent number: 7723134
    Abstract: A method of manufacturing a display device reduces damage to pad electrodes. The method includes: forming a thin film transistor in a pixel area on a first substrate and simultaneously forming a pad electrode in a pad area on the first substrate; forming a first pixel electrode connected to the thin film transistor and simultaneously forming a pad protection layer covering the pad electrode; and exposing the pad electrode by removing the pad protection layer.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: May 25, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Gyoo-Chul Jo, Chang-Soo Kim, Yun-Sik Ham
  • Publication number: 20100015747
    Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.
    Type: Application
    Filed: July 30, 2009
    Publication date: January 21, 2010
    Inventors: Doowon Kwon, Seung-Hun Shin
  • Patent number: 7638352
    Abstract: The present invention is a method of manufacturing a photoelectric conversion device having a multilayered interconnection (wiring) structure disposed on a semiconductor substrate, including steps of forming a hole in a region of the interlayer insulation film corresponding to an electrode of the transistor; burying an electroconductive substance in the hole; forming a hydrogen supplying film; conducting a thermal processing at a first temperature to supply a hydrogen from the hydrogen supplying film to the semiconductor substrate; forming the multilayered interconnection structure using Cu in a wiring material; and forming a protective film covering the multilayered interconnection structure, wherein the step of forming the multilayered interconnection structure, and the step of forming the protective film are conducted at a temperature not higher than the first temperature.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 29, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tadashi Sawayama, Takeshi Kojima
  • Publication number: 20090315136
    Abstract: A photoelectric conversion element includes a pair of electrodes, a photoelectric conversion layer provided between the pair of electrodes and a stress buffer layer provided between the photoelectric conversion layer and at least one of the electrodes, and the stress buffer layer has a stack structure comprising a crystalline sublayer.
    Type: Application
    Filed: June 19, 2009
    Publication date: December 24, 2009
    Applicant: FUJIFILM CORPORATION
    Inventor: Masayuki HAYASHI
  • Patent number: 7632701
    Abstract: A method of forming a CIGSS absorber layer includes the steps of providing a metal precursor, and selenizing the metal precursor using diethyl selenium to form a selenized metal precursor layer (CIGSS absorber layer). A high efficiency solar cell includes a CIGSS absorber layer formed by a process including selenizing a metal precursor using diethyl selenium to form the CIGSS absorber layer.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: December 15, 2009
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Neelkanth G. Dhere, Ankur A. Kadam
  • Patent number: 7545011
    Abstract: A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A first surface of the planar element is mounted to the substrate and is located to surround the semiconductor device such that the semiconductor device is aligned by the aperture. The mount further has means for mounting the semiconductor device to the substrate in an aligned position. Some embodiments include a method of making and/or using such a mount.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: June 9, 2009
    Assignee: SolFocus, Inc.
    Inventors: Stephen Horne, Gary D. Conley