Abstract: A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

Abstract: One object is to provide a transistor including an oxide semiconductor film which is used for the pixel portion of a display device and has high reliability. A display device has a first gate electrode; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode over the oxide semiconductor film; a second gate insulating film over the source electrode, the drain electrode and the oxide semiconductor film; a second gate electrode over the second gate insulating film; an organic resin film having flatness over the second gate insulating film; a pixel electrode over the organic resin film having flatness, wherein the concentration of hydrogen atoms contained in the oxide semiconductor film and measured by secondary ion mass spectrometry is less than 1×1016 cm?3.

Abstract: A highly reliable transistor in which change in electrical characteristics is suppressed is provided. A highly reliable transistor in which change in electrical characteristics is suppressed is manufactured with high productivity. A display device with less image deterioration over time is provided. An inverted staggered thin film transistor which includes, between a gate insulating film and impurity semiconductor films functioning as source and drain regions, a semiconductor stacked body including a microcrystalline semiconductor region and a pair of amorphous semiconductor regions. In the microcrystalline semiconductor region, the nitrogen concentration on the gate insulating film side is low and the nitrogen concentration in a region in contact with the amorphous semiconductor is high. Further, an interface with the amorphous semiconductor has unevenness.

Abstract: An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.

Abstract: A device that incorporates teachings of the present disclosure may include, for example, a memory array having a first array of nanotubes, a second array of nanotubes, and a resistive change material located between the first and second array of nanotubes. Other embodiments are disclosed.

Abstract: A p-type transparent oxide semiconductor includes tin oxide compounds represented by below chemical formula 1: Sn1-xMxO2??[Chemical Formula 1] wherein, in the chemical formula 1, the M is tri-valent metal and the X is a real number of 0.01˜0.05. The p-type transparent oxide semiconductor is applicable to active semiconductor devices such as TFT-LCD and transparent solar cell, due to excellent electrical and optical properties and shows superior properties in aspects of visible light transmittance (T), carrier mobility (?) and rectification ratio as well as transparency.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.

Abstract: An organic light emitting diode (OLED) display that includes a substrate, a thin film transistor, and a pixel electrode. The thin film transistor is formed on the substrate and includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The pixel electrode is electrically connected to the thin film transistor and is formed on the same layer as the source electrode and the drain electrode. The source electrode and the drain electrode include a first conductive layer, and the pixel electrode includes a first conductive layer and a second conductive layer stacked thereon.

Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

Abstract: A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate upon which the semiconductor device is to be disposed, heating the substrate to a first temperature that exceeds at least one of a softening point or glass transition temperature of the substrate, and depositing a polysilicon layer onto the substrate. A semiconductor device includes a substrate having at least one of a softening point, Ts, that is less than 600 degrees Celsius and a polysilicon layer disposed on an upper surface of the substrate such that the polysilicon layer abuts the substrate.

Abstract: Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.

Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.

Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract: An edge emitting solid state laser and method. The laser comprises at least one AlInGaN active layer on a bulk GaN substrate with a non-polar or semi-polar orientation. The edges of the laser comprise {1 1?2±6} facets. The laser has high gain, low threshold currents, capability for extended operation at high current densities, and can be manufactured with improved yield. The laser is useful for optical data storage, projection displays, and as a source for general illumination.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: A semiconductor diode is provided. The semiconductor diode includes a monocrystalline silicon semiconductor body including a first semiconductor region of a first conductivity type extending to a first surface of the semiconductor body and having a first maximum doping concentration, and a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region. The semiconductor diode further includes a polycrystalline silicon semiconductor region of the first conductivity type having a second maximum doping concentration which is higher than the first maximum doping concentration and adjoining the first semiconductor region on the first surface, a first metallization arranged on the polycrystalline silicon semiconductor region and in electric contact with the polycrystalline semiconductor region, and an edge-termination structure arranged next to the first semiconductor region. Further, a method for producing a semiconductor diode is provided.

Abstract: A composite poly-silicon substrate for solar cell having a first substrate layer and a second substrate layer is disclosed. The purity of the first substrate layer ranges from 2N to 3N. The second substrate layer is formed on the first substrate layer, and the purity of the second substrate layer ranges from 6N to 9N.

Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.

Abstract: Disclosed are thin film transistor devices incorporating a crosslinked inorganic-organic hybrid blend material as the gate dielectric. The blend material, obtained by thermally curing a mixture of an inorganic oxide precursor sol and an organosilane crosslinker at relatively low temperatures, can afford a high gate capacitance, a low leakage current density, and a smooth surface, and can be used to enable satisfactory transistor device performance at low operating voltages.

Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract: The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: Silicon nanoparticle inks provide a basis for the formation of desirable materials. Specifically, composites have been formed in thin layers comprising silicon nanoparticles embedded in an amorphous silicon matrix, which can be formed at relatively low temperatures. The composite material can be heated to form a nanocrystalline material having crystals that are non-rod shaped. The nanocrystalline material can have desirable electrical conductive properties, and the materials can be formed with a high dopant level. Also, nanocrystalline silicon pellets can be formed from silicon nanoparticles deposited form an ink in which the pellets can be relatively dense although less dense than bulk silicon. The pellets can be formed from the application of pressure and heat to a silicon nanoparticle layer.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.

Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.

Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

Abstract: A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

Abstract: A decrease in on-state current in a semiconductor device including an oxide semiconductor film is suppressed. A transistor including an oxide semiconductor film, an insulating film which includes oxygen and silicon, a gate electrode adjacent to the oxide semiconductor film, the oxide semiconductor film provided to be in contact with the insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the interface with the insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region.

Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor.

Abstract: Provided are a manufacturing method for a thin film transistor, and a thin film transistor manufactured by the manufacturing method. In the manufacturing method, a semiconductor layer and an insulating layer for stopping etching, which are sequentially stacked, are etched by dry etching and wet etching using a single photoresist pattern, and patterning the semiconductor layer and the insulating layer into a channel layer and an etch stop layer, respectively, thereby simplifying the manufacturing process of the thin film transistor.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: The present invention provides a pixel structure of a display panel and a method for manufacturing the same. The method comprises the following steps: forming a first transistor and a second transistor on a substrate, wherein the first transistor is connected between the second transistor and a data line, wherein the second transistor is connected to a first gate line and a second gate line; and forming a pixel electrode, wherein the pixel electrode is connected to the first transistor. The present invention can improve a deformation problem of signal waveforms due to delay.

Abstract: A wafer with high rupture resistance includes a plurality of surfaces, wherein the surfaces include a largest surface having a largest area than others and a side surface connected to the fringe of the largest surface. The side surface forms a nanostructured layer thereon to assist the stress dispersion of the wafer. Accordingly, the wafer is provided with a high rupture resistance so as to prevent the wafer from damages during semiconductor or other processes.

Abstract: A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 ?m, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure.

Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.

Abstract: Devices that include one or more functional semiconductor elements that are immersed in static electric fields (E-fields). In one embodiment, one or more electrets are placed proximate the one or more organic, inorganic, or hybrid semiconductor elements so that the static charge(s) of the electret(s) participate in creating the static E-field(s) that influences the semiconductor element(s). An externally applied electric field can be used, for example, to enhance charge-carrier mobility in the semiconductor element and/or to vary the width of the depletion region in the semiconductor material.

Abstract: This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass. The cover glass may be bonded to the glass substrate with an adhesive such as an epoxy, or a metal bond ring. The glass package also may include one or more signal transmission pathways between the one or more devices and the package exterior. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by surface mount technology.

Abstract: A device and a method of forming a continuous polycrystalline Ge film having crystalline Ge islands is provided that includes depositing an amorphous Ge (a-Ge) layer on a substrate, oxidizing the top surface of the a-Ge layer to form a GeOx layer, depositing a seed layer of Al on the GeOx layer and catalyzing the Al seed layer, where Ge mass transport is generated from the underlying a-Ge layer to the Al seed layer through the GeOx layer by thermal annealing, where a continuous polycrystalline Ge film having crystalline Ge islands is formed on the Al seed layer.

Abstract: Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.