Abstract: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.

Abstract: A thin film transistor array panel includes an insulating substrate, a plurality of pixel electrodes arranged on the insulating substrate in rows and columns, a plurality of thin film transistors connected with the plurality of pixel electrodes, respectively, and a plurality of gate lines and a plurality of data lines connected with the plurality of thin film transistors. When one data line and one pixel electrode which are connected with a single thin film transistor are referred to as a connected data line and a connected pixel electrode, respectively, the plurality of thin film transistors are positioned on a same side of the connected data line in two adjacent rows, and on alternating sides of the connected data line in every other two adjacent rows. Two boundary lines of the connected pixel electrode are overlapped with the connected data line.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel forming range would be formed on respective crystal regions extending from the plurality of convex end portions. A semiconductor region adjacent to the channel forming region is eliminated.

Abstract: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

Abstract: In a method of depositing a crystalline germanium layer on a substrate, a substrate is placed in the process zone comprising a pair of process electrodes. In a deposition stage, a crystalline germanium layer is deposited on the substrate by introducing a deposition gas comprising a germanium-containing gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes. In a subsequent treatment stage, the deposited crystalline germanium layer is treated by exposing the crystalline germanium layer to an energized treatment gas or by annealing the layer.

Abstract: Described herein is a device comprising: a substrate; one or more of a nanostructure extending essentially perpendicularly from the substrate; wherein the nanostructure comprises a core of a doped semiconductor, an first layer disposed on the core, and a second layer of an opposite type from the core and disposed on the first layer.

Abstract: Disclosed is a semiconductor device which includes a substrate 11, a thin film transistor 20 having a first semiconductor layer 16A that is supported by the substrate 11, a thin film diode 30 having a second semiconductor layer 16B that is supported by the substrate 11, and a metal layer 12 that is formed between the substrate 11 and the second semiconductor layer 16B. The first semiconductor layer 16A is a laterally grown crystalline semiconductor film, and the second semiconductor layer 16B is a crystalline semiconductor film that contains fine crystal grains. The average surface roughness of the second semiconductor layer 16B is higher than the average surface roughness of the first semiconductor layer 16A. Consequently, the optical sensitivity of the TFD is improved and the reliability of the TFT is improved, as compared with those in the conventional semiconductor devices.

Abstract: A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.

Abstract: A thin film transistor is provided that includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor active layer formed over the gate electrode, a fixed charge storage layer formed over a portion of the oxide semiconductor active layer, and a fixed charge control electrode formed over the fixed charged storage layer.

Abstract: Crystallization of thin films using pulsed irradiation The method includes continuously irradiating a film having an x-axis and a y-axis, in a first scan in the x-direction of the film with a plurality of line beam laser pulses to form a first set of irradiated regions, translating the film a distance in the y-direction of the film, wherein the distance is less than the length of the line beam, and continuously irradiating the film in a second scan in the negative x-direction of the film with a sequence of line beam laser pulses to form a second set of irradiated regions, wherein each of the second set of irradiated regions overlaps with a portion of the first set of irradiated regions, and wherein each of the first and the second set of irradiated regions upon cooling forms one or more crystallized regions.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: A thin film transistor (TFT) having an offset structure is disclosed. The TFT maintains a sufficiently low “off” current and a sufficiently high “on” current. The TFT includes an active region. The active region includes a gate electrode; an active layer that overlaps with the gate electrode; a gate insulating layer between the gate electrode and the active layer; and a source/drain electrode layer including source/drain electrodes that are electrically connected to the active region. Some of the source/drain electrodes overlap partially with the gate electrode. Other of the source/drain electrodes are offset from the gate electrode. The source/drain electrodes and the gate electrode are in a symmetrical arrangement.

Abstract: An organic electroluminescent device includes first and second substrates spaced apart from and facing each other, an organic electroluminescent diode on an inner surface of the second substrate, a gate line formed on an inner surface of the first substrate in a first direction, a data line formed in a second direction crossing the first direction, a power supply line spaced apart from the data line and formed in the second direction, a switching thin film transistor at a crossing portion of the gate and data lines, a driving thin film transistor at a crossing portion of the switching thin film transistor and the power supply line, a connecting electrode connected to the driving thin film transistor, and an electrical connecting pattern corresponding to the connecting electrode and for electrically connecting the connecting electrode to the organic electroluminescent diode.

Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.

Abstract: Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.

Abstract: Disclosed are thin film transistor devices incorporating a crosslinked inorganic-organic hybrid blend material as the gate dielectric. The blend material, obtained by thermally curing a mixture of an inorganic oxide precursor sol and an organosilane crosslinker at relatively low temperatures, can afford a high gate capacitance, a low leakage current density, and a smooth surface, and can be used to enable satisfactory transistor device performance at low operating voltages.

Abstract: One object is to propose a memory device in which a period in which data is held can be ensured and memory capacity per unit area can be increased. The memory device includes a memory element, a transistor including an oxide semiconductor in an active layer for control of accumulating, holding, and discharging charge in the memory element, and a capacitor connected to the memory element. At least one of a pair of electrodes of the capacitor has a light-blocking property. Further, the memory device includes a light-blocking conductive film or a light-blocking insulating film. The active layer is positioned between the electrode having a light-blocking property and the light-blocking conductive film or the light-blocking insulating film.

Abstract: A method for manufacturing a low-temperature polysilicon thin film comprises the steps of providing a substrate and forming a buffer layer on the substrate; forming a first amorphous silicon thin film on the buffer layer; forming catalyst particles on the first amorphous silicon thin film; forming a second amorphous silicon thin film to cover the first amorphous silicon thin film and the catalyst particles; and performing a crystallization of the first and second amorphous silicon thin films by using the catalyst particles so as to form the low-temperature polysilicon thin film.

Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.

Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. An oxide semiconductor film serving as a channel formation region of a transistor is formed by a sputtering method at a temperature higher than 200° C., so that the number of water molecules eliminated from the oxide semiconductor film can be 0.5/nm3 or less according to thermal desorption spectroscopy. A substance including a hydrogen atom such as hydrogen, water, a hydroxyl group, or hydride which causes variation in the electric characteristics of a transistor including an oxide semiconductor is prevented from entering the oxide semiconductor film, whereby the oxide semiconductor film can be highly purified and made to be an electrically i-type (intrinsic) semiconductor.

Abstract: A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

Abstract: A display device according to the present invention includes: a planarization layer for insulating between a gate electrode etc. and a data wiring, a drain electrode, or the like of the transistor; and a barrier layer that is formed on an upper surface or lower surface of the planarization layer and at the same time, adapted to suppress diffusion of moisture or degassing components from the planarization layer. The display device adopts a device structure effective in reducing the plasma damage on the planarization layer by devising a positional relationship between the planarization layer and the barrier layer. Also, in combination with a novel structure as a structure for a pixel electrode, effects such as an increase in luminance can be provided as well.

Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

Abstract: An electro-optical device for performing time division gray scale display and which is capable of arbitrarily setting the amount of time during which light is emitted by EL elements is provided. From among n sustain periods Ts1, . . . , Tsn, the brightness of light emitted by the EL elements during at least one sustain period is set to be always lower than the brightness of light emitted by the EL elements during the other sustain periods, and the sustain periods are extended by the amount that the brightness has dropped. In accordance with the above structure, the sustain periods can be extended by lowering the setting of the brightness of light emitted by the EL elements.

Abstract: The present disclosure relates to a device comprising a mono-crystalline substrate, the mono-crystalline substrate having at least one recessed region which exposes predetermined crystallographic planes of the mono-crystalline substrate, the at least one recessed region further having a recess width and comprising a filling material and an embedded nanochannel, wherein the width, the shape, and the depth of the embedded nanochannel is determined by the recess width of the at least one recessed region and by the growth rate of the growth front of the filling material in a direction perpendicular to the exposed predetermined crystallographic planes. The present disclosure is also related to a method for manufacturing a nanochannel device.

Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.

Abstract: In a vertical diode, an N+-type layer, an N?-type layer, and a P+-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N?-type layer is lower than the effective impurity concentrations of the N+-type layer and the P+-type layer. At least one of the N+-type layer, the N?-type layer, and the P+-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.

Abstract: Provided are a semiconductor device including a dual gate transistor and a method of fabricating the same. The semiconductor device includes a lower gate electrode, an upper gate electrode on the lower gate electrode, a contact plug interposed between the lower gate electrode and the upper gate electrode, and connecting the lower gate electrode to the upper gate electrode, and a functional electrode spaced apart from the upper gate electrode and formed at the same height as the upper gate electrode. The dual gate transistor exhibiting high field effect mobility is applied to the semiconductor device, so that characteristics of the semiconductor device can be improved. In particular, since no additional mask or deposition process is necessary, a large-area high-definition semiconductor device can be mass-produced with neither an increase in process cost nor a decrease in yield.

Abstract: The present invention provides a circuit board that includes top gate TFTs and bottom gate TFTs formed on the same substrate and that can improve reliability of these TFTs.

Abstract: A display device and a manufacturing method thereof are disclosed. In one embodiment, the display device includes 1) a substrate having a pixel region, a transistor region, and a capacitor region and 2) a transistor formed in the transistor region, wherein the transistor comprises i) an active layer formed over the substrate, ii) a gate insulating layer formed on the active layer, iii) a gate electrode formed on the gate insulating layer, and iv) a first interlayer insulating layer covering the gate electrode and formed on the gate insulating layer, v) a second interlayer insulating layer formed on the first interlayer insulating layer and vi) a source electrode and a drain electrode electrically connected to the active layer.

Abstract: An improved piezoresistive-based sensor (78) can include a cavity (66) in a substantially solid substrate (68). A reactive agent can optionally be present in the cavity (66). A flexible machined membrane can form a wall of the cavity (66). The flexible machined membrane can include an array of channels (76) configured to permit selective passage of a target material into and out of the cavity. Additionally, the flexible machined membrane can include a piezoresistive features (74) associated with the membrane. The reactive agent included in the cavity (66) can be volumetrically responsive to the presence of the target material or fluid. These sensors can be configured as pressure sensors, chemical sensors, flow sensors, and the like.

Abstract: A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided.

Abstract: Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R?W is satisfied.

Abstract: A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.

Abstract: The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.

Abstract: A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.

Abstract: Provided are a display substrate, a liquid crystal display (LCD) including the display substrate, and a method of manufacturing the display substrate. The display substrate includes: an insulating substrate; a gate wiring formed on the insulating substrate and extending generally in a first direction; a data wiring which is insulated from the gate wiring, intersects the gate wiring, and which extends generally in a second direction; a pixel electrode formed in a pixel region defined by the gate wiring and the data wiring; and a storage wiring which is formed on the same layer as the gate wiring, is overlapped by the data wiring to be insulated from the data wiring, and which extends generally in the second direction, wherein each of the gate wiring and the storage wiring has a tapered surface oriented generally at an inclination angle of approximately 30 degrees or less with respect to the insulating substrate.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.

Abstract: In a liquid crystal display device in which a liquid crystal layer exhibiting a blue phase is sandwiched between a first substrate and a second substrate, a pixel electrode layer is electrically connected to a drain electrode layer of a transistor and a common electrode layer is electrically connected to a conductive layer formed through the same steps as the drain electrode layer. The pixel electrode layer and the common electrode layer are over an interlayer film and spaced apart from each other. An opening formed in the interlayer film is filled with liquid crystal, and the liquid crystal layer is formed.

Abstract: A thin film transistor including a first polycrystalline semiconductor layer disposed on a substrate, a second polycrystalline semiconductor layer disposed on the first polycrystalline semiconductor layer, and metal catalysts configured to adjoin the first polycrystalline semiconductor layer and spaced apart from one another at specific intervals.

Abstract: The described technology relates generally to a thin film transistor comprising a gate electrode, a semiconductor layer and source/drain electrode, wherein the source/drain electrode is disposed in a range of a region in which the semiconductor layer is formed. Therefore, the present embodiments can provide a thin film transistor in which reliability is excellent because a change amount of threshold voltage is small.

Abstract: An object is to provide a transistor having a novel electrode structure capable of substantially maintaining on-state current while parasitic capacitance generated in an overlap portion between a source electrode layer (a drain electrode layer) and a gate electrode layer is reduced. Parasitic capacitance is reduced by using a source electrode layer and a drain electrode in a comb shape in a transistor. Curved current flowing from side edges of electrode tooth portions can be generated by controlling the width of an end of a comb-shaped electrode layer or the interval between the electrode tooth portions. This curved current compensates for a decrease in linear current due to a comb electrode shape; thus, on-state current can be kept unchanged even when parasitic capacitance is reduced.

Abstract: A thin film transistor using oxide semiconductor for a channel, which may be controlled such that threshold voltage is positive and may be improved in reliability is provided. The thin film transistor includes a gate electrode, a pair of source/drain electrodes, an oxide semiconductor layer forming a channel and provided between the gate electrode and the pair of source/drain electrodes, a first insulating film as a gate insulating film provided on the oxide semiconductor layer on a side near the gate electrode, and a second insulating film provided on the oxide semiconductor layer on a side near the pair of source/drain electrodes. One or both of the first insulating film and the second insulating film includes an aluminum oxide having a film density of 2.70 g/cm3 or more and less than 2.79 g/cm3.

Abstract: In connection with various example embodiments, an organic electronic device is provided with an organic material that is susceptible to decreased mobility due to the trapping of electron charge carriers in response to exposure to air. The organic material is doped with an n-type dopant that, when combined with the organic material, effects air stability for the doped organic material (e.g., exhibits a mobility that facilitates stable operation in air, such as may be similar to operation in inert environments). Other embodiments are directed to organic electronic devices n-doped and exhibiting such air stability.

Abstract: Epitaxial structures, methods of making epitaxial structures, and devices incorporating such epitaxial structures are disclosed. The methods and the structures employ a liquid-phase Group IVA semiconductor element precursor ink (e.g., including a cyclo- and/or polysilane) and have a relatively good film quality (e.g., texture, density and/or purity). The Group IVA semiconductor element precursor ink forms an epitaxial film or feature when deposited on a (poly)crystalline substrate surface and heated sufficiently for the Group IVA semiconductor precursor film or feature to adopt the (poly)crystalline structure of the substrate surface. Devices incorporating a selective emitter that includes the present epitaxial structure may exhibit improved power conversion efficiency relative to a device having a selective emitter made without such a structure due to the improved film quality and/or the perfect interface formed in regions between the epitaxial film and contacts formed on the film.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: A nanocrystalline superlattice solar cell utilizing a superlattice constructed from alternating amorphous and nanocrystalline layers is provided. The amorphous layers of the superlattice include Germanium. In one embodiment the Germanium content is homogeneous across the amorphous layer. Alternatively, the Germanium content is graded across the amorphous layer from a lower content to a greater content as the amorphous layer is grown. The grading of Germanium content can vary from 0% or greater at a boundary with the preceding layer to 100% or less at a boundary with a subsequent layer. The grading may be continuous or may occur in discreet step increases in Germanium content.

Abstract: An organic light emitting display device includes a substrate having transmitting and pixel regions, the pixel regions being separated by the transmitting regions, at least one thin film transistor in each of the pixel regions, a plurality of transparent first conductive lines electrically connected to the thin film transistors and extending across the transmitting regions, a plurality of second conductive lines electrically connected to the thin film transistors and extending across the transmitting regions, a passivation layer, a plurality of pixel electrodes on the passivation layer, the pixel electrodes being separated and positioned to correspond to respective pixel regions, each of the pixel electrodes being electrically connected to and overlapping a corresponding thin film transistor, an opposite electrode overlapping the pixel electrodes in the transmitting and pixel regions, and an organic emission layer between the pixel electrodes and the opposite electrode.

Abstract: A display device capable of implementing the light shielding effect and process simplification, and a method of manufacturing the display device. The display device includes a transistor formed in a first region on a substrate, a pixel electrode formed in a second region on the substrate, a buffer layer formed beneath the transistor in the first region, and a light shielding layer formed between the buffer layer and the substrate in the first region. In the display device, the light shielding layer may include a semiconductor material.