Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.

Abstract: A thin film transistor and a method of manufacturing the thin film transistor is disclosed. The thin film transistor includes first and second ohmic contact layers, an activation layer, an insulating layer, a source electrode formed on the insulating layer and connected to the first ohmic contact layer through first contact hole, a drain electrode formed on the insulating layer and connected to the second ohmic contact layer through second contact hole, a gate electrode formed on the insulating layer between the source electrode and the drain electrode and overlapping the activation layer, and a protective layer formed on the source electrode, the drain electrode, and the gate electrode.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.

Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.

Abstract: Laminated structures having improved optical gain are provided. In one embodiment, a laminated structure includes a first cladding layer having at least two barrier layers which have different energy band gaps, an active layer formed on the first cladding layer and having an active layer energy band gap, and a second cladding layer formed on the active layer and including at least two barrier layers which have different energy band gaps. The first cladding layer and the second cladding layer may be doped with a different type of dopant.

Abstract: A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: An article includes a polycrystalline semiconductor layer having a plurality of single crystal crystallites of semiconductor material and a substrate having a melting or softening point of <200° C. supporting the semiconductor layer. An average grain size of the plurality of single crystal crystallites is less at an interface proximate to the substrate as compared to an average grain size in the semiconductor layer remote from the interface. The semiconductor layer is fused exclusive of any bonding agent or intermediate layer to the surface of the substrate.

Abstract: A mother thin film transistor (TFT) array substrate includes an insulating substrate, at least two TFT arrays and printed wirings. The TFT array includes TFTs formed on the insulating substrate. The printed wirings are connected to the TFT arrays. The printed wiring includes a discontinuous metal layer and at least one bridge layer connecting the discontinuous metal layer. The bridge layer is made from corrosion-resistant material.

Abstract: A method of manufacturing a transistor and a method of manufacturing an organic electroluminescence display are disclosed. When an amorphous silicon layer is crystallized, a silicon oxide layer formed on a polysilicon layer is subsequently patterned. Impurity ions are implanted into first and second regions of the amorphous silicon layer to form first and second doped regions. The silicon oxide layer is patterned so that the silicon oxide layer may be removed from an ohmic contact region of the polysilicon layer, and covers only a channel region of the polysilicon layer.

Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover.

Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Abstract: Disclosed herein is a thin film transistor including: a semiconductor layer including an amorphous oxide, and a source electrode and a drain electrode which are provided in contact with the semiconductor layer. The source electrode and the drain electrode are formed by use of iridium or iridium oxide.

Abstract: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.

Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.

Abstract: In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.

Abstract: An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Abstract: Phosphorus is implanted into a crystalline semiconductor film by an ion dope method. However, a concentration of phosphorus required for gettering is 1×1020/cm3 or higher which hinders recrystallization by later anneal, and thus this becomes a problem. Also, when phosphorus is added at a high concentration, processing time required for doping is increased and throughput in a doping step is reduced, and thus this becomes a problem. The present invention is characterized in that impurity regions to which an element belonging to the group 18 of the periodic table is added are formed in a semiconductor film having a crystalline structure and gettering for segregating in the impurity regions a metal element contained in the semiconductor film is performed by heat treatment. Also, a one conductivity type impurity may be contained in the impurity regions.

Abstract: A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.

Abstract: A method of forming a localized SOI structure in a substrate (10) wherein a trench (18) is formed in the substrate, and a dielectric layer (20) is formed on the base of the trench (18). The trench is filled with semiconductor material (22) by means of epitaxial growth.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.

Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.

Abstract: A method of patterning the surface of a substrate with at least one organic semiconducting compound including: (a) providing a stamp having a surface including a plurality of indentations formed therein defining an indentation pattern contiguous with a stamping surface and defining a stamping pattern, (b) coating the stamping surface with at least one compound (C1) capable of binding to the surface of the substrate and at least one organic semiconducting compound (S), (c) contacting at least a portion of the surface of a substrate with the stamping surface to allow deposition of the compound (C1) on the substrate, (d) removing the stamping surface to provide a pattern of binding sites on the surface of the substrate, (e) applying a plurality of crystallites of the organic semiconducting compound (S) to the surface of the substrate to bind at least a portion of the applied crystallites to the binding sites on the surface of the substrate.

Abstract: Deep via trenches and deep marker trenches are formed in a bulk substrate and filled with a conductive material to form deep conductive vias and deep marker vias. At least one first semiconductor device is formed on the first surface of the bulk substrate. A disposable dielectric capping layer and a disposable material layer are formed over the first surface of the bulk substrate. The second surface, located on the opposite side of the first surface, of the bulk substrate is polished to expose and planarize the deep conductive vias and deep marker vias, which become through-substrate vias and through-substrate alignment markers, respectively. At least one second semiconductor device and second metal interconnect structures are formed on the second surface of the bulk substrate. The disposable material layer and the disposable dielectric capping layer are removed and first metal interconnect structures are formed on the first surface.

Abstract: A method for fabricating a photo sensor on an amorphous silicon thin film transistor panel includes forming a photo sensor with a bottom electrode, a silicon-rich dielectric layer, and a top electrode, such that the light sensor has a high reliability. The fabrication method is compatible with the fabrication process of a thin film transistor.

Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

Abstract: The present invention relates to multicrystalline p-type silicon wafers with high lifetime. The silicon wafers contain 0.2-2.8 ppma boron and 0.06-2.8 ppma phosphorous and/or arsenic and have been subjected to phosphorous diffusion and phosphorous gettering at a temperature of above 925° C. The invention further relates to a method for production of such multicrystalline silicon wafers and to solar cells comprising such silicon wafers.

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while baring the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.

Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film comprising adjacent primary grain boundaries that are not parallel to each other and do not contact each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.

Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.

Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type can be completed with three photomask.

Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.

Abstract: Stacked transistors and electronic devices including the stacked transistors. An electronic device includes a substrate, a first transistor on the substrate and including a first active layer, a first gate, and a first gate insulating layer between the first active layer and the first gate, a first metal line spaced apart from the first gate on the substrate, a first insulating layer covering the first transistor and the first metal line, and a second transistor on the first insulating layer between the first transistor and the first metal line, and including a second active layer, a second gate, and a second gate insulating layer between the second active layer and the second gate.

Abstract: A thin-film transistor includes a substrate, a gate electrode over the substrate, an insulating layer over the gate electrode, and a semiconductor layer over the insulating layer. The semiconductor layer includes a channel region, a source region, and a drain region. A source electrode is over the source region, and a drain electrode is over the drain region. The source electrode and the drain electrode each comprise Ni and a metal other than Ni. The channel region, the source region, and the drain region comprise at least one of a polycrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer and a microcrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer.

Abstract: A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.

Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: To achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way. In addition, to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which crystal faces and/or crystal axes of single-crystalline semiconductor layers of a first conductive MISFET and a second conductive MISFET are different. The crystal faces and/or crystal axes are arranged so that mobility of carriers flowing in channel length directions in the respective MISFETs is increased. Such a structure can increase mobility of carriers flowing through channels of the MISFETs and high speed operation of a semiconductor integrated circuit can be achieved. Further, low voltage driving becomes possible, and low power consumption can be realized.

Abstract: A method for making a thin film transistor, the method comprising the steps of: providing a growing substrate; applying a catalyst layer on the growing substrate; heating the growing substrate with the catalyst layer in a furnace with a protective gas therein, supplying a carbon source gas and a carrier gas at a ratio ranging from 100:1 to 100:10, and growing a carbon nanotube layer on the growing substrate; forming a source electrode, a drain electrode, and a gate electrode; and covering the carbon nanotube layer with an insulating layer, wherein the source electrode and the drain electrode are electrically connected to the single-walled carbon nanotube layer, the gate electrode is opposite to and electrically insulated from the single-walled carbon nanotube layer.

Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes.

Abstract: A TFT and the like capable of realizing performances such as a low threshold voltage value, high carrier mobility and a low leak current easily. A TFT consists of a polycrystalline Si film having a small heat capacity part and a large heat capacity part, and the small heat capacity part is used at least as a channel part. The polycrystalline Si film is formed of a crystal grain film through laser annealing of an energy density with which the small heat capacity part melts completely but the large heat capacity part does not melt completely. Since the channel part is formed of large crystal grains grown from the boundaries between the small heat capacity part and the large heat capacity parts, it is possible to realize performances such as a low threshold voltage value, high carrier mobility and a low leak current by using a typical laser annealing device.

Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

Abstract: The present invention relates to a thin film transistor array panel that includes an organic layer formed on a data line and a drain electrode disposed on a color filter. A thickness of a portion of the organic layer around a contact hole exposing a portion of the drain electrode is similar to a thickness of a portion of the organic layer around a contact hole exposing a portion of the data line. Having approximately the same thickness can prevent non-uniform etching of the organic layer around contact holes and deterioration of the thin film transistor array panel.

Abstract: Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas and hydrogen (H2)-containing gas. In this method, the nanocrystal silicon layer can be directly deposited on a glass substrate using plasma vapor deposition without performing a post-processing process so that the fabrication of a nonvolatile memory device can be simplified, thereby reducing fabrication cost.

Abstract: A fabrication method of the light emitting element and its light emitting element are disclosed herein. It utilizes the membrane forming technology to form optic films arranged in array on a substrate and then upward forming the epitaxial layer by the epitaxial lateral overgrowth (ELOG) technology so as to form light-emitting elements in array. The optic films contribute to the high reflection property and can sustain high temperature in the ELOG process.

Abstract: Affords GaN epitaxial wafers designed to improve production yields, as well as semiconductor devices utilizing such GaN epitaxial wafers, and methods of manufacturing such GaN epitaxial wafers and semiconductor devices. A GaN epitaxial wafer manufacturing method involving the present invention includes a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate, a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate, and a second GaN layer formation step, following the pit-formation step, of epitaxially growing a second GaN layer onto the first GaN layer, and therefore controls cracking to a minimum and improves production yields.

Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.