Abstract: A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and co

Abstract: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.

Abstract: A first electrode layer, which comes into contact with a source region, and a second electrode layer, which comes into contact with a body (back gate) region, are provided. The first and second electrode layers are insulated from each other and are extended in a direction different from an extending direction of a trench. It is possible to individually apply potentials to the first and second electrode layers, and to perform control for preventing a reverse current caused by a parasitic diode. Therefore, a bidirectional switching element can be realized by use of one MOSFET.

Abstract: A trench MOS-gated semiconductor device that includes field relief regions formed below its base region to improve its breakdown voltage, and method for its manufacturing.

Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

Abstract: In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a width larger than the uniform width. A bottom of a base region adjacent to the trench is adjacent to the second opening.

Abstract: A lateral high-voltage depletion-mode device structure in which fingers of semiconductor material are interdigitated with trench gates. Since the effective channel area is proportional to the depth of the trenches, a large amount of active channel area can be achieved for a given surface area.

Abstract: A power semiconductor device includes a substrate, a well region, a body region, a trench gate, a gate oxide layer, an L-shaped source region, an inter-layer dielectric layer and a metal layer. The body region is formed on the well region. The trench gate is formed at bilateral sides of the well region. The gate oxide layer is formed on sidewall and bottom of the trench gate. The L-shaped source region has a horizontal portion and a vertical portion formed on a portion of top region and bilateral sides of the body region, respectively. The inter-layer dielectric layer is formed on the trench gate and a portion of the L-shaped source region, thereby defining a contact window therein. The metal layer is formed on the inter-layer dielectric layer, the body region and the L-shaped source region, and connected to the L-shaped source region via the contact window.

Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow ION can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current IOFF. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

Abstract: A method for manufacturing a semiconductor device including the steps of: forming a hole having a predetermined depth in a semiconductor layer of a first conductivity type in correspondence with a drain region, the semiconductor layer being formed on a semiconductor substrate; forming a diffusion source layer containing impurities of a second conductivity type different from the first conductivity type in the hole; forming a source region of the first conductivity type in a region shallower than the depth of the hole in the semiconductor layer; forming a channel region of the second conductivity type to be disposed between the drain region and the source region in a region deeper than the depth of the source region in the semiconductor layer; and heating the semiconductor substrate to a first temperature after completing the diffusion source layer forming step to diffuse the impurities of the second conductivity type from the diffusion source layer into the channel region, thereby forming a low resistance reg